clocktop.par

一个在Xilinx spartan3实现的时钟

Constraints file: clocktop.pcf

Loading device database for application Par from file "clocktop_map.ncd".
   "clocktop" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Par from file '3s400.nph' in environment
D:/Xilinx.
Device speed data version:  PREVIEW 1.26 2003-06-19.


Resolved that IOB <N<0>> must be placed at site P96.
Resolved that IOB <N<1>> must be placed at site P95.
Resolved that IOB <N<2>> must be placed at site P94.
Resolved that IOB <N<3>> must be placed at site P93.
Resolved that IOB <N<4>> must be placed at site P85.
Resolved that IOB <N<5>> must be placed at site P76.
Resolved that IOB <N<6>> must be placed at site P62.
Resolved that IOB <N<7>> must be placed at site P61.
Resolved that IOB <P<0>> must be placed at site P102.
Resolved that IOB <P<1>> must be placed at site P101.
Resolved that IOB <P<2>> must be placed at site P100.
Resolved that IOB <P<3>> must be placed at site P97.
Resolved that IOB <b1> must be placed at site P63.
Resolved that IOB <b2> must be placed at site P64.
Resolved that IOB <b3> must be placed at site P65.
Resolved that IOB <b4> must be placed at site P71.
Resolved that IOB <clk> must be placed at site P79.


Device utilization summary:

   Number of External IOBs            17 out of 141    12%
      Number of LOCed External IOBs   17 out of 17    100%

   Number of SLICELs                 135 out of 3584    3%
   Number of SLICEMs                   8 out of 1792    1%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9899ce) REAL time: 2 secs 

Phase 3.8
..........
Phase 3.8 (Checksum:9aad75) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs 

Writing design to file clocktop.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 1145 unrouted;       REAL time: 3 secs 

Phase 2: 1069 unrouted;       REAL time: 4 secs 

Phase 3: 381 unrouted;       REAL time: 4 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 4 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         clk_BUFGP       |  BUFGMUX0| No   |   31 |  0.135     |  0.460      |
+-------------------------+----------+------+------+------------+-------------+
|      shake_sample       |   Local  |      |    2 |  0.015     |  2.078      |
+-------------------------+----------+------+------+------------+-------------+
|   shake_noshakeb4       |   Local  |      |    2 |  0.531     |  1.980      |
+-------------------------+----------+------+------+------------+-------------+
|     clockkernel_mclkbuf |   Local  |      |    7 |  0.037     |  1.528      |
+-------------------------+----------+------+------+------------+-------------+
|     clockkernel_sclkbuf |   Local  |      |    7 |  0.026     |  1.635      |
+-------------------------+----------+------+------+------------+-------------+
|     clockkernel_moncbuf |   Local  |      |    5 |  0.035     |  1.729      |
+-------------------------+----------+------+------+------------+-------------+
|   shake_noshakeb3       |   Local  |      |    3 |  0.017     |  2.120      |
+-------------------------+----------+------+------+------------+-------------+
|     clockkernel_daycbuf |   Local  |      |    7 |  0.032     |  1.674      |
+-------------------------+----------+------+------+------------+-------------+
| clockkernel_y1buf       |   Local  |      |    3 |  0.010     |  1.350      |
+-------------------------+----------+------+------+------------+-------------+
| clockkernel_y2buf       |   Local  |      |    3 |  0.000     |  1.098      |
+-------------------------+----------+------+------+------------+-------------+
| clockkernel_y3buf       |   Local  |      |    3 |  0.000     |  1.340      |
+-------------------------+----------+------+------+------------+-------------+
| clockkernel_y4buf       |   Local  |      |    2 |  0.000     |  0.529      |
+-------------------------+----------+------+------+------------+-------------+
|     clockkernel_hclkbuf |   Local  |      |    7 |  0.039     |  1.754      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 141


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.896
   The MAXIMUM PIN DELAY IS:                               4.052
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.572

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         770         270          64          38           3           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  69 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clocktop.ncd.


PAR done.