📄 clocktop.twr
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Release 6.1i Trace G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml clocktop clocktop.ncd -o
clocktop.twr clocktop.pcf
Design file: clocktop.ncd
Physical constraint file: clocktop.pcf
Device,speed: xc3s400,-4 (PREVIEW 1.26 2003-06-19)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
N<0> | 18.213(R)|clk_BUFGP | 0.000|
N<1> | 17.584(R)|clk_BUFGP | 0.000|
N<2> | 17.639(R)|clk_BUFGP | 0.000|
N<3> | 17.596(R)|clk_BUFGP | 0.000|
N<4> | 17.204(R)|clk_BUFGP | 0.000|
N<5> | 17.312(R)|clk_BUFGP | 0.000|
N<6> | 18.429(R)|clk_BUFGP | 0.000|
N<7> | 17.879(R)|clk_BUFGP | 0.000|
P<0> | 13.054(R)|clk_BUFGP | 0.000|
P<1> | 13.162(R)|clk_BUFGP | 0.000|
P<2> | 13.021(R)|clk_BUFGP | 0.000|
P<3> | 12.507(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 9.971| | | |
---------------+---------+---------+---------+---------+
Analysis completed Wed Aug 01 22:11:22 2007
--------------------------------------------------------------------------------
Peak Memory Usage: 61 MB
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