top.rpt
来自「在软件MAX+plus II环境中」· RPT 代码 · 共 858 行 · 第 1/5 页
RPT
858 行
F6 4/ 8( 50%) 1/ 8( 12%) 0/ 8( 0%) 2/2 1/2 11/22( 50%)
F7 6/ 8( 75%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 11/22( 50%)
F8 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
F9 6/ 8( 75%) 4/ 8( 50%) 0/ 8( 0%) 0/2 0/2 8/22( 36%)
F10 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 17/22( 77%)
F11 6/ 8( 75%) 3/ 8( 37%) 3/ 8( 37%) 1/2 1/2 8/22( 36%)
F12 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 13/22( 59%)
F13 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 6/22( 27%)
F14 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 2/2 1/2 7/22( 31%)
F15 8/ 8(100%) 4/ 8( 50%) 5/ 8( 62%) 0/2 0/2 8/22( 36%)
F16 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
F17 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
F18 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 16/96 ( 16%)
Total logic cells used: 987/1728 ( 57%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.59/4 ( 89%)
Total fan-in: 3547/6912 ( 51%)
Total input pins required: 10
Total input I/O cell registers required: 0
Total output pins required: 12
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 987
Total flipflops required: 345
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 124/1728 ( 7%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 8 8 0 8 1 2 8 0 8 0 0 8 8 8 8 8 8 0 8 1 8 0 0 0 8 0 8 8 5 8 0 8 0 4 0 8 165/0
B: 0 0 8 4 0 3 0 0 0 0 7 6 0 8 8 0 7 6 0 4 6 0 6 0 0 8 0 0 0 0 0 7 0 4 6 0 7 105/0
C: 8 7 0 8 8 7 0 8 5 0 8 8 8 3 8 8 2 0 0 8 8 8 8 7 8 0 0 7 7 0 8 8 8 0 8 8 0 197/0
D: 3 8 8 7 8 6 8 6 7 6 7 4 7 7 7 0 6 7 0 8 6 0 6 8 8 8 8 0 8 8 8 0 6 6 0 8 8 216/0
E: 8 7 0 0 3 7 7 8 7 8 7 0 8 6 0 6 7 0 0 8 8 0 8 8 8 8 6 4 5 6 8 8 8 0 7 0 0 189/0
F: 8 8 8 8 8 4 6 3 6 8 6 7 2 8 8 8 8 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 115/0
Total: 27 38 32 27 35 28 23 33 25 30 35 25 33 40 39 30 38 22 0 36 29 16 28 23 24 32 14 19 28 19 32 23 30 10 25 16 23 987/0
Device-Specific Information: e:\risc experiment\top.rpt
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** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
54 - - - -- INPUT G ^ 0 0 0 0 CLR
70 - - - 05 INPUT ^ 0 0 0 6 ID0
126 - - - -- INPUT ^ 0 0 0 6 ID1
125 - - - -- INPUT ^ 0 0 0 6 ID2
7 - - A -- INPUT ^ 0 0 0 6 ID3
110 - - - 02 INPUT ^ 0 0 0 6 ID4
69 - - - 06 INPUT ^ 0 0 0 6 ID5
56 - - - -- INPUT ^ 0 0 0 8 ID6
124 - - - -- INPUT ^ 0 0 0 8 ID7
55 - - - -- INPUT G ^ 0 0 0 4 Q
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\risc experiment\top.rpt
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** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
11 - - C -- OUTPUT 0 1 0 0 BS_B
82 - - F -- OUTPUT 0 1 0 0 LDAR
102 - - A -- OUTPUT 0 1 0 0 LDIR
32 - - F -- OUTPUT 0 1 0 0 LDPC
97 - - C -- OUTPUT 0 1 0 0 OD0
95 - - C -- OUTPUT 0 1 0 0 OD1
23 - - D -- OUTPUT 0 1 0 0 OD2
18 - - C -- OUTPUT 0 1 0 0 OD3
91 - - D -- OUTPUT 0 1 0 0 OD4
96 - - C -- OUTPUT 0 1 0 0 OD5
101 - - A -- OUTPUT 0 1 0 0 OD6
100 - - A -- OUTPUT 0 1 0 0 OD7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\risc experiment\top.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 25 OR2 0 4 0 2 |ALU:42|LPM_ADD_SUB:404|addcore:adder|pcarry1
- 3 - A 29 OR2 0 3 0 2 |ALU:42|LPM_ADD_SUB:404|addcore:adder|pcarry2
- 4 - A 29 OR2 0 3 0 2 |ALU:42|LPM_ADD_SUB:404|addcore:adder|pcarry3
- 5 - A 28 OR2 0 3 0 2 |ALU:42|LPM_ADD_SUB:404|addcore:adder|pcarry4
- 2 - A 28 OR2 0 3 0 2 |ALU:42|LPM_ADD_SUB:404|addcore:adder|pcarry5
- 1 - A 19 OR2 0 3 0 2 |ALU:42|LPM_ADD_SUB:404|addcore:adder|pcarry6
- 8 - E 13 OR2 0 3 0 1 |ALU:42|LPM_ADD_SUB:404|addcore:adder|pcarry7
- 7 - A 25 OR2 s 0 3 0 1 |ALU:42|LPM_ADD_SUB:404|addcore:adder|~115~1
- 7 - A 30 OR2 0 3 0 1 |ALU:42|LPM_ADD_SUB:404|addcore:adder|:116
- 5 - A 29 OR2 0 3 0 1 |ALU:42|LPM_ADD_SUB:404|addcore:adder|:117
- 8 - A 36 OR2 0 3 0 1 |ALU:42|LPM_ADD_SUB:404|addcore:adder|:118
- 6 - A 28 OR2 0 3 0 1 |ALU:42|LPM_ADD_SUB:404|addcore:adder|:119
- 8 - A 19 OR2 0 3 0 1 |ALU:42|LPM_ADD_SUB:404|addcore:adder|:120
- 7 - E 13 OR2 0 3 0 1 |ALU:42|LPM_ADD_SUB:404|addcore:adder|:121
- 8 - E 10 OR2 0 3 0 1 |ALU:42|LPM_ADD_SUB:404|addcore:adder|:122
- 5 - A 25 OR2 0 4 0 2 |ALU:42|LPM_ADD_SUB:690|addcore:adder|pcarry1
- 8 - A 30 OR2 0 3 0 2 |ALU:42|LPM_ADD_SUB:690|addcore:adder|pcarry2
- 1 - A 36 OR2 0 3 0 2 |ALU:42|LPM_ADD_SUB:690|addcore:adder|pcarry3
- 2 - A 36 OR2 0 3 0 2 |ALU:42|LPM_ADD_SUB:690|addcore:adder|pcarry4
- 7 - A 28 OR2 0 3 0 2 |ALU:42|LPM_ADD_SUB:690|addcore:adder|pcarry5
- 3 - A 19 OR2 0 3 0 2 |ALU:42|LPM_ADD_SUB:690|addcore:adder|pcarry6
- 3 - E 13 OR2 0 3 0 1 |ALU:42|LPM_ADD_SUB:690|addcore:adder|pcarry7
- 2 - A 25 OR2 s 0 3 0 1 |ALU:42|LPM_ADD_SUB:690|addcore:adder|~115~1
- 6 - A 36 OR2 0 3 0 1 |ALU:42|LPM_ADD_SUB:690|addcore:adder|:118
- 6 - A 19 OR2 0 3 0 1 |ALU:42|LPM_ADD_SUB:690|addcore:adder|:120
- 5 - E 13 OR2 0 3 0 1 |ALU:42|LPM_ADD_SUB:690|addcore:adder|:121
- 5 - A 32 AND2 0 4 0 4 |ALU:42|LPM_ADD_SUB:915|addcore:adder|:83
- 2 - A 21 AND2 0 3 0 1 |ALU:42|LPM_ADD_SUB:915|addcore:adder|:91
- 6 - A 21 AND2 0 4 0 2 |ALU:42|LPM_ADD_SUB:915|addcore:adder|:95
- 3 - A 30 OR2 0 3 0 1 |ALU:42|LPM_ADD_SUB:915|addcore:adder|:108
- 7 - A 32 OR2 0 4 0 1 |ALU:42|LPM_ADD_SUB:915|addcore:adder|:109
- 5 - A 21 OR2 0 3 0 1 |ALU:42|LPM_ADD_SUB:915|addcore:adder|:111
- 5 - E 10 OR2 0 3 0 1 |ALU:42|LPM_ADD_SUB:915|addcore:adder|:114
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