uriscram.vhd

来自「RAM存储器： 设定16 个8 位存储单元。如果read= 1 则dataout」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--------------------RAM实体-------------------------
entity ram is 
	port( datain: in std_logic_vector(7 downto 0);
	     dataout: out std_logic_vector(7 downto 0); 
             address: in std_logic_vector(7 downto 0); 
                read: in std_logic;
               write: in std_logic);
end ram;

------------------RAM结构体-------------------------

architecture behavior of ram is

type sarray is array (0 to 15) of std_logic_vector(7 downto 0);
signal mem: sarray:=(("00000001"),("00000010"),("00000011"),("00000100"),
                     ("00000101"),("00000111"),("00001000"),("00001001"),
		     ("00001010"),("00001011"),("00001100"),("00001101"),
		     ("00001110"),("00001111"),("00000000"),("00000000"));

begin
      	process(read,write,address,datain)
	begin
		if read='1' then
			dataout<=mem(conv_integer(address));
		elsif write='1' then
			mem(conv_integer(address))<=datain;
		end if;
        end process;

	end behavior;