single.v

来自「verilog 我自己写得按单脉冲发生器」· Verilog 代码 · 共 130 行

module single(clk,reset,start,data,pluse);

input  clk,reset,start;
input  [7:0]data;
output pluse;

reg  [7:0]count;
reg  sen;
reg  len;
reg  cen;
reg  pluse;
reg  [2:0]delay;
reg  [1:0]temp;
reg  [7:0]wide;


always @(posedge clk)
if ( reset =='b0 )
  begin
    delay <= 0;
    temp <=0;
    len <='b0;
  end 
else if ( delay < 4)     
    delay <= delay + 1;
else if ( temp < 1 ) 
     begin 
     temp <= temp  + 1;
     len<='b1;
     end 
else len <=0;     


always @( posedge len,negedge reset)
if ( reset == 'b0)
  wide <=0;
else  if( len =='b1) 
  wide <= data;
 


always @ (posedge clk)
if( reset =='b0) 
begin 
  cen <='b0;
  sen <='b1;
end     
else  
  begin
  if(  start && sen)
   cen <= 'b1;
  else if ( start == 'b0 && count >wide )
    begin 
      cen <= 'b0;
      sen<=0;
    end   
  end
  
 
always@( posedge clk )
if(reset == 'b0 )
  begin 
    count <= 'b0;
    pluse <= 'b0;
  end  
else  
   begin
     if( cen == 'b0)
       begin 
         count <= 'b0;
         pluse <='b0;
       end   
     else if( cen == 'b1 && count <=wide )
       begin 
         count <= count + 1;
         pluse <='b1;
       end   
     else if ( cen == 'b0 && start == 'b0 )
       begin 
        count <= 'b0;
        pluse <='b0;
       end  
       else pluse<=0;
   end

      
endmodule