dds.v

verilog 我自己写得按单脉冲发生器

module dds(clk,DATA,RB,DOUT,reset);
input   clk,RB,reset;
input   [2:0]DATA;
output  [7:0]DOUT;
reg     [10:0]temp;
reg     CLK;
reg     [2:0]count;
reg     [7:0]DOUT;
reg    [7:0]rom[255:0];
integer    i;

initial 
begin
for(i=0;i<64;i=i+1)
rom[i]=64+i;
for(i=64;i<128;i=i+1)
rom[i]=191-i;
for(i=128;i<192;i=i+1)
rom[i]=191-i;
for(i=192;i<256;i=i+1)
rom[i]=i-191;
end 


     
always@(posedge clk)
  if (!RB)
  begin 
   CLK<=0;
   count<=0;
  end
  else if(count<4)
    count<=count+3'B1;
  else  
  begin 
    count<=0;
    CLK<=~CLK;
  end 


always@(posedge CLK or RB)
 if(!RB) 
 begin 
   DOUT<=8'b0;
   temp<=11'b0;
 end   
 else 
 begin 
    temp<=DATA+temp;   
    DOUT<=rom[temp[10:3]];
 end    


endmodule