clock.fit.qmsg

一个用verilog编写的数字时钟

{ "Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "14.758 ns register pin " "Info: Estimated most critical path is register to pin delay of 14.758 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en\[7\]~reg0 1 REG LAB_X9_Y7 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y7; Fanout = 5; REG Node = 'en\[7\]~reg0'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "" { en[7]~reg0 } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.148 ns) + CELL(0.740 ns) 1.888 ns reduce_nor~1040 2 COMB LAB_X10_Y7 2 " "Info: 2: + IC(1.148 ns) + CELL(0.740 ns) = 1.888 ns; Loc. = LAB_X10_Y7; Fanout = 2; COMB Node = 'reduce_nor~1040'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "1.888 ns" { en[7]~reg0 reduce_nor~1040 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.345 ns) + CELL(0.914 ns) 3.147 ns reduce_nor~1043 3 COMB LAB_X10_Y7 2 " "Info: 3: + IC(0.345 ns) + CELL(0.914 ns) = 3.147 ns; Loc. = LAB_X10_Y7; Fanout = 2; COMB Node = 'reduce_nor~1043'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "1.259 ns" { reduce_nor~1040 reduce_nor~1043 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.896 ns) + CELL(0.740 ns) 4.783 ns reduce_nor~12 4 COMB LAB_X11_Y7 4 " "Info: 4: + IC(0.896 ns) + CELL(0.740 ns) = 4.783 ns; Loc. = LAB_X11_Y7; Fanout = 4; COMB Node = 'reduce_nor~12'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "1.636 ns" { reduce_nor~1043 reduce_nor~12 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.637 ns) + CELL(0.740 ns) 7.160 ns dataout_code\[0\]~736 5 COMB LAB_X13_Y7 1 " "Info: 5: + IC(1.637 ns) + CELL(0.740 ns) = 7.160 ns; Loc. = LAB_X13_Y7; Fanout = 1; COMB Node = 'dataout_code\[0\]~736'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "2.377 ns" { reduce_nor~12 dataout_code[0]~736 } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.511 ns) 8.343 ns dataout_code\[0\]~737 6 COMB LAB_X13_Y7 8 " "Info: 6: + IC(0.672 ns) + CELL(0.511 ns) = 8.343 ns; Loc. = LAB_X13_Y7; Fanout = 8; COMB Node = 'dataout_code\[0\]~737'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "1.183 ns" { dataout_code[0]~736 dataout_code[0]~737 } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.914 ns) 9.979 ns reduce_or~88 7 COMB LAB_X12_Y7 1 " "Info: 7: + IC(0.722 ns) + CELL(0.914 ns) = 9.979 ns; Loc. = LAB_X12_Y7; Fanout = 1; COMB Node = 'reduce_or~88'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "1.636 ns" { dataout_code[0]~737 reduce_or~88 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.457 ns) + CELL(2.322 ns) 14.758 ns dataout\[7\] 8 PIN PIN_109 0 " "Info: 8: + IC(2.457 ns) + CELL(2.322 ns) = 14.758 ns; Loc. = PIN_109; Fanout = 0; PIN Node = 'dataout\[7\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "4.779 ns" { reduce_or~88 dataout[7] } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.881 ns 46.63 % " "Info: Total cell delay = 6.881 ns ( 46.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.877 ns 53.37 % " "Info: Total interconnect delay = 7.877 ns ( 53.37 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "14.758 ns" { en[7]~reg0 reduce_nor~1040 reduce_nor~1043 reduce_nor~12 dataout_code[0]~736 dataout_code[0]~737 reduce_or~88 dataout[7] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 4 " "Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 4%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 13:48:22 2006 " "Info: Processing ended: Sat Feb 18 13:48:22 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0}  } {  } 0}