clock.map.rpt

一个用verilog编写的数字时钟

;     -- Total 1-input functions    ; 42      ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 74      ;
; Total logic cells in carry chains ; 42      ;
; I/O pins                          ; 18      ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 74      ;
; Total fan-out                     ; 651     ;
; Average fan-out                   ; 3.39    ;
+-----------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                      ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |clock                     ; 174 (174)   ; 74           ; 0          ; 18   ; 0            ; 100 (100)    ; 39 (39)           ; 35 (35)          ; 42 (42)         ; |clock              ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 74    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 74    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 32    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; en[1]~reg0                             ; 7       ;
; en[2]~reg0                             ; 5       ;
; en[7]~reg0                             ; 5       ;
; en[5]~reg0                             ; 5       ;
; en[4]~reg0                             ; 7       ;
; en[3]~reg0                             ; 7       ;
; en[6]~reg0                             ; 7       ;
; dataout_buf[6][1]                      ; 5       ;
; dataout_buf[7][0]                      ; 5       ;
; Total number of inverted registers = 9 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 8:1                ; 4 bits    ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |clock|dataout_code[0]     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Feb 18 13:48:05 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 1 design units, including 1 entities, in source file clock.v
    Info: Found entity 1: clock
Info: Elaborating entity "clock" for the top level hierarchy
Warning: Verilog HDL assignment warning at clock.v(18): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clock.v(19): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clock.v(20): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clock.v(21): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clock.v(22): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clock.v(23): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clock.v(28): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at clock.v(32): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at clock.v(67): truncated value with size 32 to match size of target (26)
Warning: Verilog HDL assignment warning at clock.v(69): truncated value with size 32 to match size of target (26)
Warning: Verilog HDL assignment warning at clock.v(71): truncated value with size 32 to match size of target (26)
Warning: Verilog HDL assignment warning at clock.v(77): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(78): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(79): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(80): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(81): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(82): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(83): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(84): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(89): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(91): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(93): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(95): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(97): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(99): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(101): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(103): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(105): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(107): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(109): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock.v(111): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL Always Construct warning at clock.v(74): variable "dataout_buf[2]" may not be assigned a new value in every possible path through the Always Construct.  Variable "dataout_buf[2]" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at clock.v(74): variable "dataout_buf[5]" may not be assigned a new value in every possible path through the Always Construct.  Variable "dataout_buf[5]" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Registers with preset signals will power-up high
Info: Implemented 192 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 16 output pins
    Info: Implemented 174 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 33 warnings
    Info: Processing ended: Sat Feb 18 13:48:10 2006
    Info: Elapsed time: 00:00:06