📄 low_cost_design_authentication_for_spartan_3e.vhd
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-- Example of cost effective design authentication using the unique 64-bit
-- serial number of the Intel StrataFlash NOR FLASH Memory.
--
-- Design provided and tested on the Spartan-3E Starter Kit.
--
-- Ken Chapman - Xilinx Ltd - 14th November 2006.
--
--
-- The design employs PicoBlaze (KCPSM3) to perform an authentication algorithm as well
-- as present authentication status information on the LCD display. Unlike a full production
-- design, this PicoBlaze also allows the authentication to be validated or cleared
-- for evaluation purposes using simple commands sent over an RS232 UART connection to DCE
-- (J9). HyperTerminal or similar should be used with settings 9600 baud, 8-bit, no parity,
-- 1 stop-bit and flow control = NONE.
--
-- IMPORTANT NOTE: A full production design should not compromise security by making
-- the presence of a design authentication algorithm obviously visible and certainly
-- should not provide helpful information or override controls as presented in this
-- reference evaluation design. This design is intended to provide stimulus for your
-- own creativity and should not be used directly in a production design.
--
-- A second PicoBlaze processor is used to control the 8 LEDs. This simple function is
-- representative of a 'real design' which the Spartan-3E would be implementing and
-- therefore becomes the design which is actually authorised to work or disabled
-- depending on the results of the security checks. In an authorised design the LEDs will
-- be sequenced in a repeated pattern using PWM techniques. An unauthorsied design will
-- produce undesirable LED behaviour!
--
-- The design also includes and example of an anti-tampering circuit which detects
-- in the program for the PicoBlaze performing the security algorithm has been modified.
-- If the program has been modified then this will also prevent the design from operating.
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2006. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Furthermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
--
entity low_cost_design_authentication_for_spartan_3e is
Port ( led : out std_logic_vector(7 downto 0);
tx_female : out std_logic;
rx_female : in std_logic;
lcd_d : inout std_logic_vector(7 downto 4);
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_e : out std_logic;
strataflash_oe : out std_logic;
strataflash_ce : out std_logic;
strataflash_we : out std_logic;
strataflash_byte : out std_logic;
strataflash_sts : in std_logic; --Pullup on input
strataflash_a : out std_logic_vector(23 downto 0);
strataflash_d : inout std_logic_vector(7 downto 0);
platformflash_oe : out std_logic;
spi_rom_cs : out std_logic;
spi_adc_conv : out std_logic;
spi_dac_cs : out std_logic;
spi_sck : out std_logic;
clk_50mhz : in std_logic);
end low_cost_design_authentication_for_spartan_3e;
--
------------------------------------------------------------------------------------
--
-- Start of test architecture
--
architecture Behavioral of low_cost_design_authentication_for_spartan_3e is
--
------------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------------
--
--
--
-- declaration of KCPSM3
--
component kcpsm3
Port ( address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- declaration of program ROM for 'real application'
--
component led_ctrl
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
--proc_reset : out std_logic; --additional port on JTAG Loader version
clk : in std_logic);
end component;
--
-- declaration of program ROM for authentication algorithm
--
component security
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
check_address : in std_logic_vector(10 downto 0); --additional access port for content verification
check_data : out std_logic_vector(8 downto 0);
clk : in std_logic);
end component;
--
-- declaration of UART transmitter with integral 16 byte FIFO buffer.
--
component uart_tx
Port ( data_in : in std_logic_vector(7 downto 0);
write_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end component;
--
-- declaration of UART Receiver with integral 16 byte FIFO buffer
--
component uart_rx
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
read_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end component;
--
-- 'Bucket Brigade' 16-byte FIFO Buffer
--
component bbfifo_16x8
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- SIGNALS
--
-- These are divided into two sections.
--
-- First the signals associated with the 'real application'. In a typical real design
-- there would be many more signals in this section.
--
-- Second are the signals involved in the design authentication process. In this
-- design they are more abundant than normal due to the evaluation and demonstration
-- objectives of this reference design.
--
------------------------------------------------------------------------------------
-- Application Signals
------------------------------------------------------------------------------------
--
-- Signals used to connect application KCPSM3 processor to program ROM
--
signal application_address : std_logic_vector(9 downto 0);
signal application_instruction : std_logic_vector(17 downto 0);
signal application_port_id : std_logic_vector(7 downto 0);
signal application_out_port : std_logic_vector(7 downto 0);
signal application_in_port : std_logic_vector(7 downto 0);
signal application_write_strobe : std_logic;
signal application_read_strobe : std_logic;
signal application_interrupt : std_logic :='0';
signal application_interrupt_ack : std_logic;
signal application_kcpsm3_reset : std_logic;
--
-- Signals for interrupt generation used for PWM timing
--
signal application_interrupt_count : integer range 0 to 195 :=0;
signal application_interrupt_event : std_logic;
--
--
-- Signals for connection of peripherals to the application processor
--
signal led_drive : std_logic_vector(7 downto 0);
signal link_fifo_data : std_logic_vector(7 downto 0);
signal read_link_fifo : std_logic;
signal reset_link_fifo : std_logic;
signal link_fifo_buffer_full : std_logic;
signal link_fifo_half_full : std_logic;
signal link_fifo_data_present : std_logic;
signal write_link_fifo : std_logic; --actually driven by security processor
--
------------------------------------------------------------------------------------
-- Authentication Security Signals
------------------------------------------------------------------------------------
--
--
-- Authentication enable/disable signals.
-- Includes main clock which can also be disabled to bring entire device to a halt.
--
signal clk : std_logic;
signal security_disable_interrupts : std_logic :='0';
signal security_disable_outputs : std_logic :='0';
signal security_disable_clock : std_logic :='0';
--
-- Signals used to connect security KCPSM3 processor to program ROM
--
signal security_address : std_logic_vector(9 downto 0);
signal security_instruction : std_logic_vector(17 downto 0);
signal security_port_id : std_logic_vector(7 downto 0);
signal security_out_port : std_logic_vector(7 downto 0);
signal security_in_port : std_logic_vector(7 downto 0);
signal security_write_strobe : std_logic;
signal security_read_strobe : std_logic;
signal security_interrupt : std_logic :='0';
signal security_interrupt_ack : std_logic;
signal security_kcpsm3_reset : std_logic;
--
--
-- Signals for connection of peripherals to the security processor
--
signal psuedo_random_lfsr_counter : std_logic_vector(16 downto 1);
--
-- Signals for connection of UART
--
signal baud_count : integer range 0 to 325 :=0;
signal en_16_x_baud : std_logic;
signal write_to_uart : std_logic;
signal tx_full : std_logic;
signal tx_half_full : std_logic;
signal read_from_uart : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal rx_data_present : std_logic;
signal rx_full : std_logic;
signal rx_half_full : std_logic;
--
--
-- Signals to connect to StrataFLASH memory
--
signal strataflash_read : std_logic;
signal write_data : std_logic_vector(7 downto 0);
--
--
-- Signals for LCD connection
--
signal lcd_rw_control : std_logic;
signal lcd_output_data : std_logic_vector(7 downto 4);
signal lcd_drive : std_logic;
--
-- Signals to perform anti-tampering function
--
signal anti_tamper_address : std_logic_vector(10 downto 0) :="00000000000";
signal anti_tamper_data : std_logic_vector(8 downto 0);
signal anti_tamper_compute : std_logic_vector(15 downto 0) :="0000000000000000";
--
--
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
begin
--
--
----------------------------------------------------------------------------------------------------------------------------------
-- Disable unused components on the Spartan-3E Starter Kit
----------------------------------------------------------------------------------------------------------------------------------
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