timer20bit.vhd

来自「基于spartan3e的LCD显示程序,可直接将其bit文件烧写到spartan」· VHDL 代码 · 共 160 行

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:28:16 06/26/2006 
-- Design Name: 
-- Module Name:    timer30bit - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity timer20bit is
    Port ( timerout : out  STD_LOGIC;
           Clock : in  STD_LOGIC;
           Enable : in  STD_LOGIC;
           Data : in  STD_LOGIC_VECTOR (19 downto 0);
           Load : in  STD_LOGIC;
			  Reset : in  STD_LOGIC
			  );
end timer20bit;

architecture Behavioral of timer20bit is
	signal tmr0 :std_logic_vector (19 downto 0);
	signal precarry19:std_logic;
	signal precarry15:std_logic;
	signal precarry7:std_logic;
	signal precarry7a:std_logic;
	signal timerout_ctrl:std_logic;
	signal timerout_buf:std_logic;
	signal Enable1 :std_logic;

begin

 process( Clock ) is
  begin
		if Clock'event and Clock = '1' then
      if Reset = '1' then-------------------reset
        tmr0(7 downto 0) <= (others=>'0');
		elsif Load = '1' then-----------------preset
		  tmr0(7 downto 0) <= Data(7 downto 0);
      elsif Enable1= '1' then-------------------enable
		  tmr0(7 downto 0)<= tmr0(7 downto 0)+1;
      end if;
		end if;
  end process;
 
 --timer0---15:8
 process( Clock ) is
  begin
		if Clock'event and Clock = '1' then
      if Reset = '1' then-------------------reset
        tmr0(15 downto 8) <= (others=>'0');
		elsif Load = '1' then-----------------preset
		  tmr0(15 downto 8) <= Data(15 downto 8);
      elsif Enable1= '1' and precarry7= '1' then-------------------enable
		  tmr0(15 downto 8)<= tmr0(15 downto 8)+1;
      end if;
		end if;
  end process;
 --timer0---19:16
 process( Clock ) is
  begin
		if Clock'event and Clock = '1' then
      if Reset = '1' then-------------------reset
        tmr0(19 downto 16) <= (others=>'0');
		elsif Load = '1' then
		  tmr0(19 downto 16) <= Data(19 downto 16);
      elsif Enable1= '1' and precarry15 = '1' and precarry7= '1' then-------------------enable
		  tmr0(19 downto 16)<= tmr0(19 downto 16)+1;
      end if;
		end if;
  end process;
  --Precarry---precarry29/precarry23/precarry15/precarry7
 process( Clock) is
  begin
		if Clock'event and Clock = '1' then
      
		if Reset = '1' then-------------------reset
        precarry19 <= '0';
		elsif tmr0(19 downto 16) = "1111"  then
		  precarry19 <= '1';
		else
		  precarry19 <= '0';
		end if;
		
		if Reset = '1' then-------------------reset
        precarry15 <= '0';
		elsif tmr0(15 downto 8) = "11111111"  then
		  precarry15 <= '1';
		else
		  precarry15 <= '0';
		end if;
		
		if Reset = '1' then-------------------reset
        precarry7 <= '0';
		elsif tmr0(7 downto 0) = "11111110"  then
		  precarry7 <= '1';
		else
		  precarry7 <= '0';
		end if;
		
		if Reset = '1' then-------------------reset
        precarry7a <= '0';
		elsif tmr0(7 downto 0) = "11111101"  then
		  precarry7a <= '1';
		else
		  precarry7a <= '0';
		end if;
		
		end if;
  end process;
 


 process( Clock ) is
  begin
		if Clock'event and Clock = '1' then
      if Reset = '1' or timerout_ctrl='1' then-------------------reset
        timerout_buf <= '0';
		elsif (precarry19 = '1' and precarry15= '1' and precarry7a= '1') then
		  timerout_buf<= '1';
      end if;
		end if;
  end process;
  
 process( Clock ) is
  begin
		if Clock'event and Clock = '1' then
      if Reset = '1' then-------------------reset
        timerout_ctrl <= '0';
		else
		  timerout_ctrl<= timerout_buf;
      end if;
		end if;
  end process;
  
  
  timerout <= timerout_buf;
  Enable1 <=tmr0(19);
end Behavioral;