user_logic.vhd

基于spartan3e的LCD显示程序,可直接将其bit文件烧写到spartan3e里面即可使用

timer2_Load <= load_clr1;--user_reg1(21);
timer2_Enable <= Delay_ctrl;
--timer2_Data <= user_reg1(0 to 19);
timer2_Data <= user_reg1(0 to 19) when (user_reg1(19)='1') else timer2_Data0;--delay control by user [80000---FFFFF(20ns---10.48ms)/50MHz CLK]
timer2_Data0 <= X"FF600" when (Delay_mux ='0') else X"EB400";        --51us/1800us
Delay_mux <= '1' when (user_reg1(22 to 29)="00000000" ) else '0';
led <= user_reg1(0 to 7);

	strata_CE <= '1';
	lcd_DATA_T<= lcd_OE1;
  lcd_DATA_O <= lcd_DATA0;
  lcd_DATA0 <= user_reg1(24 to 27) when (lcd_MUX = '1') else user_reg1(28 to 31);
  lcd_E<= lcd_E1;
  lcd_RW<= lcd_RW0;
  lcd_RS<= lcd_RS0;
  lcd_RW0<= user_reg1(23);
  lcd_RS0<= user_reg1(22);
 statemachine0:fsm1 port map
  (
   CLK			=>Bus2IP_Clk,
	RESET			=>Bus2IP_Reset,
   CTRL0			=> user_reg1(20),--AUTO/MANU
	CTRL1			=> load_clr1,--user_reg1(21),--Load
	CTRL2			=> T1us,--T1us
	CTRL3			=> timer2_out,
--	RS				=> lcd_RS0,
	RW				=> lcd_RW0,
	lcd_E			=> lcd_E1,
	OE				=> lcd_OE1,
	H_L			=> lcd_MUX,
	RD_H			=> RD_H,
	RD_L			=> RD_L,	
	Delay_ctrl  => Delay_ctrl
  );
 


--process( Bus2IP_Clk ) is
--  begin
--
--    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
--      if Bus2IP_Reset = '1' then
--		 rd_reg<=(others=>'0');
--		else
--			if RD_H = '1' then
--			rd_reg(7 downto 4)<=lcd_DATA_I;
--			end if;
--			if RD_L = '1' then
--			rd_reg(3 downto 0)<=lcd_DATA_I;
--			end if;
--		end if;
--	end if;
--  end process ;
  
process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' then
		 load_clr0<='0';
		else load_clr0<=user_reg0(0);
		end if;
    end if;
  end process ;

--Load Flag for Timer0;
 process( Bus2IP_Clk ,load_clr0 ) is
  begin
--		if load_clr0 ='1' then user_reg0(0) <= '0';
      if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' or load_clr0 ='1' then user_reg0(0) <= '0';
      elsif user_reg_write_select = "10" then
                user_reg0(0) <=  Bus2IP_Data(0);
		end if;
    end if;
  end process;
  
--Timer1 ---T=1us

process( Bus2IP_Clk ) is
  begin
    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' or timer1="110001" or load_clr1 = '1'  then
		timer1<= (others=>'0');
		else timer1 <= timer1 + 1;
		end if;
    end if;
  end process ;
--T1us
process( Bus2IP_Clk ) is
  begin
    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' or load_clr1 = '1' then
		 T1us<= '0';
		elsif timer1 = "110001" then T1us <='1';
		else T1us <= '0';
		end if;
    end if;
  end process ;




  USER_REG0_WRITE_PROC : process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' then
        user_reg0(1 to 31) <= (others =>'0');
      elsif user_reg_write_select ="10" then
        user_reg0(1 to 31) <= Bus2IP_Data(1 to 31);
      end if;
    end if;
  end process USER_REG0_WRITE_PROC;


--State Machine Load Ctrl
process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' then
		 load_clr1<='0';
		else load_clr1<=user_reg1(21);
		end if;
    end if;
  end process ;

--Load Flag for State Machine;
 process( Bus2IP_Clk ,load_clr1) is
  begin
      if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' or load_clr1 ='1'  then user_reg1(21) <= '0';
      elsif user_reg_write_select = "01" then
                user_reg1(21) <=  Bus2IP_Data(21);
		end if;
    end if;
  end process;

  USER_REG1_WRITE_PROC : process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' then
        user_reg1(0 to 20) <= (others =>'0');
        user_reg1(22 to 31) <= (others =>'0');
      elsif user_reg_write_select ="01" then
        user_reg1(0 to 20) <= Bus2IP_Data(0 to 20);
        user_reg1(22 to 31) <= Bus2IP_Data(22 to 31);
      end if;
    end if;
  end process USER_REG1_WRITE_PROC;

  ------------------------------------------
  -- Example code to read/write user logic slave model s/w accessible registers
  -- 
  -- Note:
  -- The example code presented here is to show you one way of reading/writing
  -- software accessible registers implemented in the user logic slave model.
  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
  -- to one software accessible register by the top level template. For example,
  -- if you have four 32 bit software accessible registers in the user logic, you
  -- are basically operating on the following memory mapped registers:
  -- 
  --    Bus2IP_WrCE or   Memory Mapped
  --       Bus2IP_RdCE   Register
  --            "1000"   C_BASEADDR + 0x0
  --            "0100"   C_BASEADDR + 0x4
  --            "0010"   C_BASEADDR + 0x8
  --            "0001"   C_BASEADDR + 0xC
  -- 
  --
  
  ------------------------------------------
  -- instantiate the OPB IPIF
  ------------------------------------------

  user_reg_write_select <= Bus2IP_WrCE(0 to 1);
  user_reg_read_select  <= Bus2IP_RdCE(0 to 1);
  user_write_ack        <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
  user_read_ack         <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);

--  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
--  begin
--
--    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
--      if Bus2IP_Reset = '1' then
--        user_reg0 <= (others => '0');
--        user_reg1 <= (others => '0');
--      else
--        case user_reg_write_select is
--          when "10" =>
--            for byte_index in 0 to (C_DWIDTH/8)-1 loop
--              if ( Bus2IP_BE(byte_index) = '1' ) then
--                user_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
--              end if;
--            end loop;
--          when "01" =>
--            for byte_index in 0 to (C_DWIDTH/8)-1 loop
--              if ( Bus2IP_BE(byte_index) = '1' ) then
--                user_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
--              end if;
--            end loop;
--          when others => null;
--        end case;
--      end if;
--    end if;
--
--  end process SLAVE_REG_WRITE_PROC;

  -- implement slave model register read mux
  -- A MUX, No Latches or registers are allowed to be generated below!!! 
  SLAVE_REG_READ_PROC : process( user_reg_read_select, user_reg0, user_reg1 ) is
  begin

    case user_reg_read_select is
      when "10" => user_ip2bus_data <= user_reg0(0 to 23) & rd_reg;
      when "01" => user_ip2bus_data <= int1 & user_reg1( 1 to 31);
      when others => user_ip2bus_data <= (others => '0');
---!!! A pure Mux and default to all '0',no latch allowed!!! or it may mask IPIF registers
    end case;

  end process SLAVE_REG_READ_PROC;
	

process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' or Delay_ctrl='0' then
		 int_ctrl<='0';
		elsif timer2_out='1' then 
		int_ctrl<='1';
		end if;
    end if;
  end process ;

process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' or  timer2_out = '1' then
		 int1<='0';
		elsif user_reg1(21) = '1' then
		int1<='1';
		end if;
    end if;
  end process ;
  interrupt(0) <= timer0_out;
  interrupt(1) <= '0';-----------timer2_out;
 -- interrupt(2) <= '0';
  
  IP2Bus_IntrEvent <= interrupt;


  ------------------------------------------
  -- Example code to drive IP to Bus signals
  ------------------------------------------
  IP2Bus_Data        <= user_ip2bus_data;

  IP2Bus_Ack         <= user_write_ack or user_read_ack;
  IP2Bus_Error       <= '0';
  IP2Bus_Retry       <= '0';
  IP2Bus_ToutSup     <= '0';
  
end IMP;