user_logic.vhd

基于spartan3e的LCD显示程序,可直接将其bit文件烧写到spartan3e里面即可使用

------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.            **
-- **                                                                       **
-- ** Xilinx, Inc.                                                          **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
-- ** FOR A PARTICULAR PURPOSE.                                             **
-- **                                                                       **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename:          user_logic.vhd
-- Version:           1.00.a
-- Description:       User logic.
-- Date:              Fri Jun 23 10:28:48 2006 (by Create and Import Peripheral Wizard)
-- VHDL Standard:     VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
--   active low signals:                    "*_n"
--   clock signals:                         "clk", "clk_div#", "clk_#x"
--   reset signals:                         "rst", "rst_n"
--   generics:                              "C_*"
--   user defined types:                    "*_TYPE"
--   state machine next state:              "*_ns"
--   state machine current state:           "*_cs"
--   combinatorial signals:                 "*_com"
--   pipelined or register delay signals:   "*_d#"
--   counter signals:                       "*cnt*"
--   clock enable signals:                  "*_ce"
--   internal version of output port:       "*_i"
--   device pins:                           "*_pin"
--   ports:                                 "- Names begin with Uppercase"
--   processes:                             "*_PROCESS"
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------

-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
--   C_DWIDTH                     -- User logic data bus width
--   C_NUM_CE                     -- User logic chip enable bus width
--   C_IP_INTR_NUM                -- User logic number of interrupt event
--
-- Definition of Ports:
--   Bus2IP_Clk                   -- Bus to IP clock
--   Bus2IP_Reset                 -- Bus to IP reset
--   IP2Bus_IntrEvent             -- IP to Bus interrupt event
--   Bus2IP_Data                  -- Bus to IP data bus for user logic
--   Bus2IP_BE                    -- Bus to IP byte enables for user logic
--   Bus2IP_RdCE                  -- Bus to IP read chip enable for user logic
--   Bus2IP_WrCE                  -- Bus to IP write chip enable for user logic
--   IP2Bus_Data                  -- IP to Bus data bus for user logic
--   IP2Bus_Ack                   -- IP to Bus acknowledgement
--   IP2Bus_Retry                 -- IP to Bus retry response
--   IP2Bus_Error                 -- IP to Bus error response
--   IP2Bus_ToutSup               -- IP to Bus timeout suppress
------------------------------------------------------------------------------

entity user_logic is
  generic
  (
    -- ADD USER GENERICS BELOW THIS LINE ---------------
    --USER generics added here
    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    C_DWIDTH                       : integer              := 32;
    C_NUM_CE                       : integer              := 2;
    C_IP_INTR_NUM                  : integer              := 2
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here


	 lcd_DATA_O	:out std_logic_vector ( 7 downto 4 );
--	 lcd_DATA_I	:in std_logic_vector ( 7 downto 4 );
	 lcd_DATA_T	:out std_logic;
	 lcd_E		:out std_logic;
	 lcd_RS		:out std_logic;
	 lcd_RW		:out std_logic;
	 strata_CE	:out std_logic;
	 led			:out std_logic_vector (7 downto 0);

    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    Bus2IP_Clk                     : in  std_logic;
    Bus2IP_Reset                   : in  std_logic;
    IP2Bus_IntrEvent               : out std_logic_vector(0 to C_IP_INTR_NUM-1);
    Bus2IP_Data                    : in  std_logic_vector(0 to C_DWIDTH-1);
    Bus2IP_BE                      : in  std_logic_vector(0 to C_DWIDTH/8-1);
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_CE-1);
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_CE-1);
    IP2Bus_Data                    : out std_logic_vector(0 to C_DWIDTH-1);
    IP2Bus_Ack                     : out std_logic;
    IP2Bus_Retry                   : out std_logic;
    IP2Bus_Error                   : out std_logic;
    IP2Bus_ToutSup                 : out std_logic
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
  component timer30bit
   port
  (
	 timerout	:out std_logic;
	 Clock		:in std_logic;
	 Enable		:in std_logic;
	 Data			:in std_logic_vector ( 29 downto 0 );
	 Load			:in std_logic;
	 Reset		:in std_logic
  );
  end component;



  component fsm1
  port
  (
   CLK			:in std_logic;
   RESET			:in std_logic;
   CTRL0			:in std_logic;--Auto/Manu
	CTRL1			:in std_logic;--Load
	CTRL2			:in std_logic;--T1us
	CTRL3			:in std_logic;--T40us
--	RS				:in std_logic;
	RW				:in std_logic;
	lcd_E			:out std_logic;
	OE				:out std_logic;
	H_L			:out std_logic;
	RD_H			:out std_logic;
	RD_L			:out std_logic;
	Delay_ctrl  :out std_logic
   );
  end component;
  component timer20bit
   port
  (
	 timerout	:out std_logic;
	 Clock		:in std_logic;
	 Enable		:in std_logic;
	 Data			:in std_logic_vector ( 19 downto 0 );
	 Load			:in std_logic;
	 Reset		:in std_logic
  );
  end component;
  
	
	
  
  --USER signal declarations added here, as needed for user logic
	signal lcd_DATA0	:std_logic_vector (7 downto 4);
  ------------------------------------------
  -- Signals for user logic slave model s/w accessible register example
  ------------------------------------------
  signal user_reg0                       : std_logic_vector(0 to C_DWIDTH-1);
  signal user_reg1                       : std_logic_vector(0 to C_DWIDTH-1);
  signal user_reg_write_select           : std_logic_vector(0 to 1);
  signal user_reg_read_select            : std_logic_vector(0 to 1);
  signal user_ip2bus_data                : std_logic_vector(0 to C_DWIDTH-1);
  signal user_read_ack                   : std_logic;
  signal user_write_ack                  : std_logic;
  signal lcd_RW0 			                 : std_logic;
  signal lcd_RS0 			                 : std_logic;
  signal lcd_E0 			                 : std_logic;
  signal lcd_RW1 			                 : std_logic;
  signal lcd_RS1 			                 : std_logic;
  signal lcd_E1 			                 : std_logic;
  signal lcd_OE1 			                 : std_logic;
  signal lcd_MUX 			                 : std_logic;

	signal timer0_out		:std_logic;
	signal timer0_Enable	:std_logic;
	signal timer0_Data	:std_logic_vector (29 downto 0);
	signal timer0_Load	:std_logic;
	signal load_clr0		:std_logic;
	
	signal load_clr1		:std_logic;  	
   signal timer1	:std_logic_vector (5 downto 0);
	signal T1us :std_logic;
	signal RD_H :std_logic;
	signal RD_L :std_logic;
	signal rd_reg:std_logic_vector (7 downto 0);
	

	signal timer2_out		:std_logic;
	signal timer2_Enable	:std_logic;
	signal timer2_Data	:std_logic_vector (19 downto 0);
	signal timer2_Data0	:std_logic_vector (19 downto 0);
	signal timer2_Load	:std_logic;
	signal load_clr2		:std_logic;
	signal Delay_ctrl		:std_logic;
	signal Delay_mux		:std_logic;
	signal int_ctrl		:std_logic;
	signal int1				:std_logic;
  ------------------------------------------
  -- Signals for user logic interrupt example
  ------------------------------------------
  signal interrupt                      : std_logic_vector(0 to C_IP_INTR_NUM-1);

begin

  --USER logic implementation added here

timer0:timer30bit  port map
  (
	 timerout	=>timer0_out,
	 Clock		=>Bus2IP_Clk,
	 Enable		=>timer0_Enable,
	 Data			=>timer0_Data,
	 Load			=>timer0_Load,
	 Reset		=>Bus2IP_Reset
  );

timer0_Load <= user_reg0(0);
timer0_Enable <= user_reg0(1);
timer0_Data <= user_reg0(2 to 31);





timer2:timer20bit  port map
  (
	 timerout	=>timer2_out,
	 Clock		=>Bus2IP_Clk,
	 Enable		=>timer2_Enable,
	 Data			=>timer2_Data,
	 Load			=>timer2_Load,
	 Reset		=>Bus2IP_Reset
  );