fsm_rw.vhd

来自「基于spartan3e的LCD显示程序,可直接将其bit文件烧写到spartan」· VHDL 代码 · 共 191 行

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:56:53 06/26/2006 
-- Design Name: 
-- Module Name:    fsm_RW - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fsm1 is
    Port ( CLK : in  STD_LOGIC;
           RESET : in  STD_LOGIC;
           CTRL0 : in  STD_LOGIC;--4/8
           CTRL1 : in  STD_LOGIC;--load
           CTRL2 : in  STD_LOGIC;--T1us
           CTRL3 : in  STD_LOGIC;--T40/1600us
--           RS : in  STD_LOGIC;
           RW : in  STD_LOGIC;
           lcd_E : out  STD_LOGIC;
           OE : out  STD_LOGIC;
           H_L : out  STD_LOGIC;
           RD_H : out  STD_LOGIC;
           RD_L : out  STD_LOGIC;
           Delay_ctrl : out  STD_LOGIC
			  );
end fsm1;



architecture Behavioral of fsm1 is
--type state is (st0,st_wr1,st_wr2,st_wr3,st_wr4,st_rd1,st_rd2,st_rd3,st_rd4);
--signal curr_state,next_state:state;
	signal   counter     :  std_logic_vector(2 downto 0);
	signal   STOP     	:  std_logic;

begin

process (CLK,RESET) is
begin
	if CLK'event and CLK ='1' then
	if (RESET = '1') or CTRL1 = '1' then
		counter <= "000";
		elsif CTRL2='1' and ( counter/="111") then --- and STOP = '0' then
			counter <= counter +1;
		end if;
	end if;
end process;
process (CLK,RESET) is
begin
	if (RESET = '1') or CTRL1 = '1' then
		lcd_E <= '0';
		OE	 	<= '0';
		H_L	<= '1';
		Delay_ctrl <= '0';
		STOP <= '0';
	elsif CLK'event and CLK ='1' then
--Write to LCD
           lcd_E	<='0';
           OE		<='0';
           H_L		<='1';
           RD_H 	<='0';
           RD_L 	<='0';
           Delay_ctrl <='0';
			  STOP	<='0';
		if RW = '0' then
			case counter is
				when "000"	=> OE <= '1';	lcd_E<='1';
				when "001"	=> OE <= '1';lcd_E<='1';
				when "010"	=> OE <= '1';
				
				when "011"	=> OE <= '1';
					if CTRL0 ='1'	then		
					H_L <='0' ;
					end if;
				when "100"	=> 
					if CTRL0 = '1' then
					H_L <='0' ;lcd_E <='1';OE <= '1';Delay_ctrl <='1';STOP <='1';
					end if;
				when "101"	=> Delay_ctrl <='1';				
					if CTRL3 ='1' then STOP <= '1';end if;
					if CTRL0 ='1' then lcd_E<='1'; H_L <='0' ;OE <='1';end if;

				when "110"	=> Delay_ctrl <='1'; if CTRL0 ='1' then H_L <='0' ;OE <='1';end if;
				when others	=>
			end case;
		else
			case counter is
				when "000"	=>
				when "001"	=>
				when "010"	=>
				when "011"	=>
				when "100"	=>
				when "101"	=>
				when "110"	=>
				when others	=> 
			end case;
		end if;
	end if;

end process;

--process (CLK,RESET) is
--begin
--	if (RESET = '1') then
--		curr_state<=st0;
--	elsif CLK'event and CLK = '1' then
--		if CTRL2 = '1' then
--		curr_state <= next_state;
--		end if;
--	end if;
--end process;

--process (curr_state,CTRL0,CTRL1,CTRL2,CTRL3,RW) is
--begin
--	lcd_E <= '0';
--	OE <= '0';
--	H_L <= '1';
--	RD_H <='0';
--	RD_L <='0';
--	Delay_ctrl <= '0';
--case curr_state is
--	when st0 =>
--		if CTRL1 ='1' then
--			if RW = '0' then
--				next_state <= st_wr1;
--			else
--				next_state <= st_rd1;
--				RD_H <= '1';
--			end if;
--			
--		end if;
--	when st_rd1 =>
--		lcd_E <= '1';
--		next_state <= st_rd2;
--	when st_rd2 =>
--		next_state <= st_rd3;
--	when st_rd3 =>
--		next_state <= st_rd4;
--		RD_L <='1';
--	when st_rd4 =>
--		if CTRL3='1' then
--			next_state <= st0;
--		end if;
--	when st_wr1 =>
--		if CTRL0 = '1' then
--			next_state<= st_wr2;
--		else
--			next_state <= st_wr4;
--			Delay_ctrl <= '1';
--		end if;
--	when st_wr2 =>
--			next_state<= st_wr3;
--			lcd_E <= '1';
--	when st_wr3 =>
--			next_state<= st_wr4;
--			
--	when st_wr4 =>
--		Delay_ctrl <= '1';
--		if CTRL3='1' then
--			next_state <= st0;
--		end if;
--	when others => 
--		next_state <= st0;
--	
--	
--	
--end process;

end Behavioral;