fsm1.syr

基于spartan3e的LCD显示程序,可直接将其bit文件烧写到spartan3e里面即可使用

Release 8.1.03i - xst I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 3.29 s | Elapsed : 0.00 / 3.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 3.29 s | Elapsed : 0.00 / 3.00 s
 
--> Reading design: fsm1.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "fsm1.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "fsm1"
Output Format                      : NGC
Target Device                      : xc3s100e-5-vq100

---- Source Options
Top Module Name                    : fsm1
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : fsm1.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/MicroBlaze/s3esk_lcd/pcores/s3esk_lcd_v1_00_a/devl/fsm/fsm_RW1.vhd" in Library work.
Entity <fsm1> compiled.
Entity <fsm1> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <fsm1> (Architecture <Behavioral>).
WARNING:Xst:819 - "E:/MicroBlaze/s3esk_lcd/pcores/s3esk_lcd_v1_00_a/devl/fsm/fsm_RW1.vhd" line 58: The following signals are missing in the process sensitivity list:
   CTRL1.
WARNING:Xst:819 - "E:/MicroBlaze/s3esk_lcd/pcores/s3esk_lcd_v1_00_a/devl/fsm/fsm_RW1.vhd" line 68: The following signals are missing in the process sensitivity list:
   CTRL1.
INFO:Xst:1304 - Contents of register <RD_H> in unit <fsm1> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <RD_L> in unit <fsm1> never changes during circuit operation. The register is replaced by logic.
Entity <fsm1> analyzed. Unit <fsm1> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fsm1>.
    Related source file is "E:/MicroBlaze/s3esk_lcd/pcores/s3esk_lcd_v1_00_a/devl/fsm/fsm_RW1.vhd".
    Found 4x1-bit ROM for signal <$n0020>.
    Found 1-bit register for signal <lcd_E>.
    Found 1-bit register for signal <OE>.
    Found 1-bit register for signal <H_L>.
    Found 1-bit register for signal <Delay_ctrl>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0011>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0012>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0016>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0024>.
    Found 3-bit up counter for signal <counter>.
    Found 1-bit register for signal <STOP>.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
	inferred   5 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <fsm1> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 4x1-bit ROM                                           : 1
# Counters                                             : 1
 3-bit up counter                                      : 1
# Registers                                            : 5
 1-bit register                                        : 5
# Multiplexers                                         : 4
 1-bit 4-to-1 multiplexer                              : 4

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 4x1-bit ROM                                           : 1
# Counters                                             : 1
 3-bit up counter                                      : 1
# Registers                                            : 5
 Flip-Flops                                            : 5
# Multiplexers                                         : 4
 1-bit 4-to-1 multiplexer                              : 4

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx.

Optimizing unit <fsm1> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fsm1, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : fsm1.ngr
Top Level Output File Name         : fsm1
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 13

Cell Usage :
# BELS                             : 17
#      GND                         : 1
#      INV                         : 1
#      LUT2                        : 3
#      LUT2_L                      : 3
#      LUT3                        : 3
#      LUT4                        : 1
#      LUT4_L                      : 4
#      MUXF5                       : 1
# FlipFlops/Latches                : 8
#      FDC                         : 4
#      FDCE                        : 3
#      FDP                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 6
#      OBUF                        : 6
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s100evq100-5 

 Number of Slices:                       7  out of    960     0%  
 Number of Slice Flip Flops:             8  out of   1920     0%  
 Number of 4 input LUTs:                14  out of   1920     0%  
 Number of bonded IOBs:                 13  out of     66    19%  
 Number of GCLKs:                        1  out of     24     4%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 8     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 4.185ns (Maximum Frequency: 238.929MHz)
   Minimum input arrival time before clock: 3.805ns
   Maximum output required time after clock: 4.364ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 4.185ns (frequency: 238.929MHz)
  Total number of paths / destination ports: 34 / 11
-------------------------------------------------------------------------
Delay:               4.185ns (Levels of Logic = 2)
  Source:            counter_0 (FF)
  Destination:       counter_0 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: counter_0 to counter_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             9   0.514   1.024  counter_0 (counter_0)
     LUT4_L:I1->LO         1   0.612   0.169  _n00151 (N4)
     LUT2:I1->O            3   0.612   0.771  _n00152 (_n0015)
     FDCE:CE                   0.483          counter_0
    ----------------------------------------
    Total                      4.185ns (2.221ns logic, 1.964ns route)
                                       (53.1% logic, 46.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
  Total number of paths / destination ports: 13 / 8
-------------------------------------------------------------------------
Offset:              3.805ns (Levels of Logic = 2)
  Source:            CTRL2 (PAD)
  Destination:       counter_0 (FF)
  Destination Clock: CLK rising

  Data Path: CTRL2 to counter_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.106   0.833  CTRL2_IBUF (CTRL2_IBUF)
     LUT2:I0->O            3   0.612   0.771  _n00152 (_n0015)
     FDCE:CE                   0.483          counter_0
    ----------------------------------------
    Total                      3.805ns (2.201ns logic, 1.604ns route)
                                       (57.8% logic, 42.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset:              4.364ns (Levels of Logic = 1)
  Source:            lcd_E (FF)
  Destination:       lcd_E (PAD)
  Source Clock:      CLK rising

  Data Path: lcd_E to lcd_E
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.514   0.681  lcd_E (lcd_E_OBUF)
     OBUF:I->O                 3.169          lcd_E_OBUF (lcd_E)
    ----------------------------------------
    Total                      4.364ns (3.683ns logic, 0.681ns route)
                                       (84.4% logic, 15.6% route)

=========================================================================
CPU : 19.36 / 23.21 s | Elapsed : 19.00 / 23.00 s
 
--> 

Total memory usage is 135212 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    3 (   0 filtered)
Number of infos    :    2 (   0 filtered)