s3esk_lcd.syr

基于spartan3e的LCD显示程序,可直接将其bit文件烧写到spartan3e里面即可使用

Release 8.1.03i - xst I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 4.03 s | Elapsed : 0.00 / 4.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 4.03 s | Elapsed : 0.00 / 4.00 s
 
--> Reading design: s3esk_lcd.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "s3esk_lcd.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "s3esk_lcd"
Output Format                      : NGC
Target Device                      : xc2vp7-6-fg456

---- Source Options
Top Module Name                    : s3esk_lcd
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : s3esk_lcd.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut4.vhd" in Library proc_common_v2_00_a.
Architecture implementation of Entity inferred_lut4 is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_bit.vhd" in Library proc_common_v2_00_a.
Architecture implementation of Entity pf_counter_bit is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit.vhd" in Library proc_common_v2_00_a.
Architecture implementation of Entity pf_adder_bit is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.vhd" in Library proc_common_v2_00_a.
Architecture implementation of Entity pf_counter is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter.vhd" in Library proc_common_v2_00_a.
Architecture implementation of Entity pf_occ_counter is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit.vhd" in Library proc_common_v2_00_a.
Architecture imp of Entity counter_bit is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" in Library proc_common_v2_00_a.
WARNING:HDLParsers:3534 - "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" Line 382. In the function Get_RLOC_Name, not all control paths contain a return statement.
WARNING:HDLParsers:3534 - "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" Line 397. In the function Get_Reg_File_Area, not all control paths contain a return statement.
Architecture proc_common_pkg of Entity proc_common_pkg is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd" in Library proc_common_v2_00_a.
Architecture implementation of Entity pf_occ_counter_top is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_top.vhd" in Library proc_common_v2_00_a.
Architecture implementation of Entity pf_counter_top is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd" in Library proc_common_v2_00_a.
Architecture implementation of Entity pf_adder is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.vhd" in Library proc_common_v2_00_a.
Architecture implementation of Entity srl16_fifo is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_select.vhd" in Library proc_common_v2_00_a.
Architecture implementation of Entity pf_dpram_select is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd" in Library proc_common_v2_00_a.
Architecture ipif_pkg of Entity ipif_pkg is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_cntr_ai.vhd" in Library proc_common_v2_00_a.
Architecture imp of Entity direct_path_cntr_ai is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd" in Library proc_common_v2_00_a.
Architecture imp of Entity counter is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" in Library proc_common_v2_00_a.
Architecture imp of Entity pselect is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd" in Library proc_common_v2_00_a.
Architecture implementation of Entity or_muxcy is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd" in Library proc_common_v2_00_a.
Architecture imp of Entity ipif_steer is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd" in Library proc_common_v2_00_a.
Architecture family of Entity family is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd" in Library wrpfifo_v1_01_b.
Architecture implementation of Entity pf_dly1_mux is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd" in Library wrpfifo_v1_01_b.
Architecture implementation of Entity ipif_control_wr is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd" in Library wrpfifo_v1_01_b.
Architecture implementation of Entity wrpfifo_dp_cntl is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.vhd" in Library rdpfifo_v1_01_b.
Architecture implementation of Entity ipif_control_rd is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.vhd" in Library rdpfifo_v1_01_b.
Architecture implementation of Entity rdpfifo_dp_cntl is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd" in Library opb_ipif_v3_01_c.
Architecture imp of Entity srl_fifo3 is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd" in Library opb_ipif_v3_01_c.
Architecture implementation of Entity opb_flex_addr_cntr is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd" in Library opb_ipif_v3_01_c.
Architecture implementation of Entity opb_be_gen is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd" in Library opb_ipif_v3_01_c.
Architecture implementation of Entity brst_addr_cntr is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd" in Library opb_ipif_v3_01_c.
Architecture implementation of Entity brst_addr_cntr_reg is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd" in Library opb_ipif_v3_01_c.
Architecture implementation of Entity write_buffer is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd" in Library opb_ipif_v3_01_c.
Architecture implementation of Entity reset_mir is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interrupt_control.vhd" in Library interrupt_control_v1_00_a.
Architecture implementation of Entity interrupt_control is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd" in Library rdpfifo_v1_01_b.
Architecture implementation of Entity rdpfifo_top is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd" in Library wrpfifo_v1_01_b.
Architecture implementation of Entity wrpfifo_top is up to date.
Compiling vhdl file "E:/MicroBlaze/s3esk_lcd/pcores/s3esk_lcd_v1_00_a/hdl/vhdl/timer30bit.vhd" in Library work.
Entity <timer30bit> compiled.
Entity <timer30bit> (Architecture <behavioral>) compiled.
Compiling vhdl file "E:/MicroBlaze/s3esk_lcd/pcores/s3esk_lcd_v1_00_a/hdl/vhdl/timer20bit.vhd" in Library work.
Architecture behavioral of Entity timer20bit is up to date.
Compiling vhdl file "E:/MicroBlaze/s3esk_lcd/pcores/s3esk_lcd_v1_00_a/hdl/vhdl/fsm_RW.vhd" in Library work.
Architecture behavioral of Entity fsm1 is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" in Library opb_ipif_v3_01_c.
Architecture implementation of Entity opb_bam is up to date.
Compiling vhdl file "C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd" in Library opb_ipif_v3_01_c.
Architecture imp of Entity opb_ipif is up to date.
Compiling vhdl file "E:/MicroBlaze/s3esk_lcd/pcores/s3esk_lcd_v1_00_a/hdl/vhdl/user_logic.vhd" in Library s3esk_lcd_v1_00_a.
Entity <user_logic> compiled.
ERROR:HDLParsers:164 - "E:/MicroBlaze/s3esk_lcd/pcores/s3esk_lcd_v1_00_a/hdl/vhdl/user_logic.vhd" Line 328. parse error, unexpected ELSIF
--> 

Total memory usage is 119548 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    3 (   0 filtered)
Number of infos    :    0 (   0 filtered)