hdpdeps.ref

基于spartan3e的LCD显示程序,可直接将其bit文件烧写到spartan3e里面即可使用

V3 60
FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd 2006/06/20.08:44:54 I.27
EN opb_ipif_v3_01_c/opb_bam 1151357726 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd \
      PB ieee/std_logic_1164 1140839709 PH ieee/NUMERIC_STD 1140839720 \
      LB proc_common_v2_00_a PB proc_common_v2_00_a/proc_common_pkg 1151357665 \
      PB proc_common_v2_00_a/ipif_pkg 1151357677
AR opb_ipif_v3_01_c/opb_bam/implementation 1151357727 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd \
      EN opb_ipif_v3_01_c/opb_bam 1151357726 LB unisim PH unisim/VCOMPONENTS 1142233852 \
      LB proc_common_v2_00_a PB proc_common_v2_00_a/proc_common_pkg 1151357665 \
      PB proc_common_v2_00_a/family 1151357689 EN proc_common_v2_00_a/pselect 1151357682 \
      EN proc_common_v2_00_a/or_muxcy 1151357684 PB proc_common_v2_00_a/ipif_pkg 1151357677 \
      EN proc_common_v2_00_a/IPIF_Steer 1151357686 PH ieee/NUMERIC_STD 1140839720 \
      PB ieee/std_logic_misc 1140839719 LB opb_ipif_v3_01_c \
      EN opb_ipif_v3_01_c/reset_mir 1151357712 EN opb_ipif_v3_01_c/brst_addr_cntr 1151357706 \
      EN opb_ipif_v3_01_c/brst_addr_cntr_reg 1151357708 \
      EN opb_ipif_v3_01_c/opb_be_gen 1151357704 LB interrupt_control_v1_00_a \
      EN interrupt_control_v1_00_a/interrupt_control 1151357714 LB wrpfifo_v1_01_b \
      EN wrpfifo_v1_01_b/wrpfifo_top 1151357718 LB rdpfifo_v1_01_b \
      EN rdpfifo_v1_01_b/rdpfifo_top 1151357716 CP proc_common_v2_00_a/pselect \
      CP std_logic      CP opb_ipif_v3_01_c/opb_be_gen \
      CP opb_ipif_v3_01_c/brst_addr_cntr CP opb_ipif_v3_01_c/brst_addr_cntr_reg \
      CP opb_ipif_v3_01_c/write_buffer CP integer CP std_logic_vector \
      CP proc_common_v2_00_a/or_muxcy CP proc_common_v2_00_a/IPIF_Steer \
      CP opb_ipif_v3_01_c/reset_mir CP natural \
      CP interrupt_control_v1_00_a/interrupt_control CP FDRE \
      CP rdpfifo_v1_01_b/rdpfifo_top CP wrpfifo_v1_01_b/wrpfifo_top
FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd 2006/04/12.22:13:42 I.27
EN opb_ipif_v3_01_c/opb_ipif 1151357728 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd \
      PB ieee/std_logic_1164 1140839709 PH ieee/NUMERIC_STD 1140839720 \
      LB proc_common_v2_00_a PB proc_common_v2_00_a/ipif_pkg 1151357677 \
      PB proc_common_v2_00_a/proc_common_pkg 1151357665 LB opb_ipif_v3_01_c \
      EN opb_ipif_v3_01_c/opb_bam 1151357726
AR opb_ipif_v3_01_c/opb_ipif/imp 1151357729 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd \
      EN opb_ipif_v3_01_c/opb_ipif 1151357728 CP opb_ipif_v3_01_c/opb_bam
FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd 2006/04/12.22:13:42 I.27
EN opb_ipif_v3_01_c/write_buffer 1151357710 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd \
      PB ieee/std_logic_1164 1140839709 PH ieee/NUMERIC_STD 1140839720 \
      PB ieee/STD_LOGIC_UNSIGNED 1140839715 PB ieee/std_logic_misc 1140839719 \
      LB proc_common_v2_00_a PB proc_common_v2_00_a/proc_common_pkg 1151357665 \
      EN proc_common_v2_00_a/Counter 1151357680 LB unisim PH unisim/VCOMPONENTS 1142233852 \
      LB opb_ipif_v3_01_c EN opb_ipif_v3_01_c/srl_fifo3 1151357700
AR opb_ipif_v3_01_c/write_buffer/implementation 1151357711 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd \
      EN opb_ipif_v3_01_c/write_buffer 1151357710 CP opb_ipif_v3_01_c/srl_fifo3 \
      CP proc_common_v2_00_a/counter
FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd 2006/01/07.13:28:16 I.27
EN opb_ipif_v3_01_c/srl_fifo3 1151357700 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd \
      LB unisim         PB ieee/std_logic_1164 1140839709 PB ieee/std_logic_arith 1140839711 \
      PH unisim/VCOMPONENTS 1142233852
AR opb_ipif_v3_01_c/srl_fifo3/imp 1151357701 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd \
      EN opb_ipif_v3_01_c/srl_fifo3 1151357700 CP FDR CP MUXCY_L CP XORCY      CP FDRE \
      CP SRL16E
FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd 2006/01/07.13:28:16 I.27
EN opb_ipif_v3_01_c/brst_addr_cntr 1151357706 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd \
      PB ieee/std_logic_1164 1140839709
AR opb_ipif_v3_01_c/brst_addr_cntr/implementation 1151357707 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd \
      EN opb_ipif_v3_01_c/brst_addr_cntr 1151357706 LB proc_common_v2_00_a \
      PB proc_common_v2_00_a/proc_common_pkg 1151357665 \
      EN proc_common_v2_00_a/direct_path_cntr_ai 1151357678 LB unisim \
      PH unisim/VCOMPONENTS 1142233852 CP proc_common_v2_00_a/direct_path_cntr_ai
FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd 2006/04/12.22:13:42 I.27
EN opb_ipif_v3_01_c/opb_be_gen 1151357704 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd \
      PB ieee/std_logic_1164 1140839709 LB proc_common_v2_00_a \
      PB proc_common_v2_00_a/proc_common_pkg 1151357665
AR opb_ipif_v3_01_c/opb_be_gen/implementation 1151357705 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd \
      EN opb_ipif_v3_01_c/opb_be_gen 1151357704 LB unisim PH unisim/VCOMPONENTS 1142233852 \
      CP FDRE           CP MUXCY
FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd 2006/01/07.13:28:16 I.27
EN opb_ipif_v3_01_c/brst_addr_cntr_reg 1151357708 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd \
      PB ieee/std_logic_1164 1140839709 PB ieee/std_logic_arith 1140839711 \
      LB opb_ipif_v3_01_c EN opb_ipif_v3_01_c/opb_flex_addr_cntr 1151357702 \
      LB unisim         PH unisim/VCOMPONENTS 1142233852
AR opb_ipif_v3_01_c/brst_addr_cntr_reg/implementation 1151357709 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd \
      EN opb_ipif_v3_01_c/brst_addr_cntr_reg 1151357708 CP std_logic_vector \
      CP FDRE           CP opb_ipif_v3_01_c/opb_flex_addr_cntr
FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd 2006/01/07.13:28:16 I.27
EN opb_ipif_v3_01_c/opb_flex_addr_cntr 1151357702 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd \
      PB ieee/std_logic_1164 1140839709 PH ieee/NUMERIC_STD 1140839720 LB unisim \
      PH unisim/VCOMPONENTS 1142233852
AR opb_ipif_v3_01_c/opb_flex_addr_cntr/implementation 1151357703 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd \
      EN opb_ipif_v3_01_c/opb_flex_addr_cntr 1151357702 CP LUT4 CP MUXCY CP XORCY \
      CP FDRE
FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd 2006/01/07.13:28:16 I.27
EN opb_ipif_v3_01_c/reset_mir 1151357712 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd \
      PB ieee/std_logic_1164 1140839709 PB ieee/std_logic_arith 1140839711
AR opb_ipif_v3_01_c/reset_mir/implementation 1151357713 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd \
      EN opb_ipif_v3_01_c/reset_mir 1151357712 CP std_logic_vector