hdpdeps.ref

基于spartan3e的LCD显示程序,可直接将其bit文件烧写到spartan3e里面即可使用

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FL C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd 2006/01/07.13:25:46 I.27
EN wrpfifo_v1_01_b/wrpfifo_dp_cntl 1151357694 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd \
      PB ieee/std_logic_1164 1140839709 PB ieee/std_logic_arith 1140839711 \
      PB ieee/STD_LOGIC_UNSIGNED 1140839715 LB proc_common_v2_00_a \
      EN proc_common_v2_00_a/pf_counter_top 1151357668 \
      EN proc_common_v2_00_a/pf_occ_counter_top 1151357666 \
      EN proc_common_v2_00_a/pf_adder 1151357670
AR wrpfifo_v1_01_b/wrpfifo_dp_cntl/implementation 1151357695 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd \
      EN wrpfifo_v1_01_b/wrpfifo_dp_cntl 1151357694 CP std_logic \
      CP transition_state_type CP std_logic_vector CP pf_dly1_mux \
      CP pf_occ_counter_top CP pf_counter_top CP Boolean    CP pf_adder
FL C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd 2006/01/07.13:25:46 I.27
EN wrpfifo_v1_01_b/wrpfifo_top 1151357718 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd \
      PB ieee/std_logic_1164 1140839709 PB ieee/std_logic_arith 1140839711 \
      LB proc_common_v2_00_a EN proc_common_v2_00_a/pf_dpram_select 1151357674 \
      EN proc_common_v2_00_a/srl16_fifo 1151357672
AR wrpfifo_v1_01_b/wrpfifo_top/implementation 1151357719 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd \
      EN wrpfifo_v1_01_b/wrpfifo_top 1151357718 CP ipif_control_wr CP Integer \
      CP Boolean        CP In             CP Out            CP wrpfifo_dp_cntl \
      CP pf_dpram_select CP srl16_fifo
FL C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd 2006/01/07.13:25:46 I.27
EN wrpfifo_v1_01_b/pf_dly1_mux 1151357690 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd \
      PB ieee/std_logic_1164 1140839709 LB proc_common_v2_00_a \
      EN proc_common_v2_00_a/inferred_lut4 1151357652 LB unisim \
      PH unisim/VCOMPONENTS 1142233852
AR wrpfifo_v1_01_b/pf_dly1_mux/implementation 1151357691 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd \
      EN wrpfifo_v1_01_b/pf_dly1_mux 1151357690 CP inferred_lut4 CP FDRE
FL C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd 2006/01/07.13:25:46 I.27
EN wrpfifo_v1_01_b/ipif_control_wr 1151357692 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd \
      PB ieee/std_logic_1164 1140839709 PB ieee/std_logic_arith 1140839711
AR wrpfifo_v1_01_b/ipif_control_wr/implementation 1151357693 \
      FL C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd \
      EN wrpfifo_v1_01_b/ipif_control_wr 1151357692 CP std_logic_vector CP Integer