lock.tan.rpt

以QuatusⅡ为平台

; N/A           ; None        ; -2.977 ns ; keyin[4]  ; key[0]    ; clk      ;
; N/A           ; None        ; -2.977 ns ; keyin[4]  ; key[6]    ; clk      ;
; N/A           ; None        ; -2.977 ns ; keyin[4]  ; key[3]    ; clk      ;
; N/A           ; None        ; -2.977 ns ; keyin[4]  ; key[7]    ; clk      ;
; N/A           ; None        ; -2.977 ns ; keyin[4]  ; key[2]    ; clk      ;
; N/A           ; None        ; -2.977 ns ; keyin[4]  ; key[1]    ; clk      ;
; N/A           ; None        ; -2.977 ns ; keyin[4]  ; key[5]    ; clk      ;
; N/A           ; None        ; -3.035 ns ; keyin[3]  ; key[0]    ; clk      ;
; N/A           ; None        ; -3.035 ns ; keyin[3]  ; key[6]    ; clk      ;
; N/A           ; None        ; -3.035 ns ; keyin[3]  ; key[4]    ; clk      ;
; N/A           ; None        ; -3.035 ns ; keyin[3]  ; key[7]    ; clk      ;
; N/A           ; None        ; -3.035 ns ; keyin[3]  ; key[2]    ; clk      ;
; N/A           ; None        ; -3.035 ns ; keyin[3]  ; key[1]    ; clk      ;
; N/A           ; None        ; -3.035 ns ; keyin[3]  ; key[5]    ; clk      ;
; N/A           ; None        ; -3.230 ns ; keyin[6]  ; key[0]    ; clk      ;
; N/A           ; None        ; -3.230 ns ; keyin[6]  ; key[4]    ; clk      ;
; N/A           ; None        ; -3.230 ns ; keyin[6]  ; key[3]    ; clk      ;
; N/A           ; None        ; -3.230 ns ; keyin[6]  ; key[7]    ; clk      ;
; N/A           ; None        ; -3.230 ns ; keyin[6]  ; key[2]    ; clk      ;
; N/A           ; None        ; -3.230 ns ; keyin[6]  ; key[1]    ; clk      ;
; N/A           ; None        ; -3.230 ns ; keyin[6]  ; key[5]    ; clk      ;
; N/A           ; None        ; -3.270 ns ; lockoff   ; lockflag  ; clk      ;
; N/A           ; None        ; -3.271 ns ; lockoff   ; ledr~reg0 ; clk      ;
; N/A           ; None        ; -3.711 ns ; lockon    ; ledr~reg0 ; clk      ;
; N/A           ; None        ; -3.805 ns ; keychange ; key[0]    ; clk      ;
; N/A           ; None        ; -3.805 ns ; keychange ; key[6]    ; clk      ;
; N/A           ; None        ; -3.805 ns ; keychange ; key[4]    ; clk      ;
; N/A           ; None        ; -3.805 ns ; keychange ; key[3]    ; clk      ;
; N/A           ; None        ; -3.805 ns ; keychange ; key[7]    ; clk      ;
; N/A           ; None        ; -3.805 ns ; keychange ; key[2]    ; clk      ;
; N/A           ; None        ; -3.805 ns ; keychange ; key[1]    ; clk      ;
; N/A           ; None        ; -3.805 ns ; keychange ; key[5]    ; clk      ;
; N/A           ; None        ; -3.901 ns ; lockon    ; lockflag  ; clk      ;
; N/A           ; None        ; -3.993 ns ; lockoff   ; ledg~reg0 ; clk      ;
; N/A           ; None        ; -4.531 ns ; lockon    ; key[0]    ; clk      ;
; N/A           ; None        ; -4.531 ns ; lockon    ; key[6]    ; clk      ;
; N/A           ; None        ; -4.531 ns ; lockon    ; key[4]    ; clk      ;
; N/A           ; None        ; -4.531 ns ; lockon    ; key[3]    ; clk      ;
; N/A           ; None        ; -4.531 ns ; lockon    ; key[7]    ; clk      ;
; N/A           ; None        ; -4.531 ns ; lockon    ; key[2]    ; clk      ;
; N/A           ; None        ; -4.531 ns ; lockon    ; key[1]    ; clk      ;
; N/A           ; None        ; -4.531 ns ; lockon    ; key[5]    ; clk      ;
; N/A           ; None        ; -4.624 ns ; lockon    ; ledg~reg0 ; clk      ;
+---------------+-------------+-----------+-----------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Web Edition
    Info: Processing started: Wed Jan 09 14:57:52 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lock -c lock --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 272.63 MHz between source register "key[0]" and destination register "key[5]" (period= 3.668 ns)
    Info: + Longest register to register delay is 3.449 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y18_N15; Fanout = 1; REG Node = 'key[0]'
        Info: 2: + IC(0.472 ns) + CELL(0.447 ns) = 0.919 ns; Loc. = LCCOMB_X64_Y18_N28; Fanout = 1; COMB Node = 'equal~92'
        Info: 3: + IC(0.474 ns) + CELL(0.447 ns) = 1.840 ns; Loc. = LCCOMB_X64_Y18_N2; Fanout = 3; COMB Node = 'equal~96'
        Info: 4: + IC(0.271 ns) + CELL(0.428 ns) = 2.539 ns; Loc. = LCCOMB_X64_Y18_N24; Fanout = 8; COMB Node = 'key[0]~7'
        Info: 5: + IC(0.237 ns) + CELL(0.673 ns) = 3.449 ns; Loc. = LCFF_X64_Y18_N1; Fanout = 1; REG Node = 'key[5]'
        Info: Total cell delay = 1.995 ns ( 57.84 % )
        Info: Total interconnect delay = 1.454 ns ( 42.16 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.681 ns
            Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.070 ns) + CELL(0.548 ns) = 2.681 ns; Loc. = LCFF_X64_Y18_N1; Fanout = 1; REG Node = 'key[5]'
            Info: Total cell delay = 1.493 ns ( 55.69 % )
            Info: Total interconnect delay = 1.188 ns ( 44.31 % )
        Info: - Longest clock path from clock "clk" to source register is 2.681 ns
            Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.070 ns) + CELL(0.548 ns) = 2.681 ns; Loc. = LCFF_X64_Y18_N15; Fanout = 1; REG Node = 'key[0]'
            Info: Total cell delay = 1.493 ns ( 55.69 % )
            Info: Total interconnect delay = 1.188 ns ( 44.31 % )
    Info: + Micro clock to output delay of source is 0.255 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "ledg~reg0" (data pin = "lockon", clock pin = "clk") is 4.758 ns
    Info: + Longest pin to register delay is 7.475 ns
        Info: 1: + IC(0.000 ns) + CELL(0.805 ns) = 0.805 ns; Loc. = PIN_G26; Fanout = 3; PIN Node = 'lockon'
        Info: 2: + IC(5.414 ns) + CELL(0.447 ns) = 6.666 ns; Loc. = LCCOMB_X64_Y18_N10; Fanout = 2; COMB Node = 'ledg~14'
        Info: 3: + IC(0.443 ns) + CELL(0.280 ns) = 7.389 ns; Loc. = LCCOMB_X64_Y18_N16; Fanout = 1; COMB Node = 'ledg~15'
        Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 7.475 ns; Loc. = LCFF_X64_Y18_N17; Fanout = 1; REG Node = 'ledg~reg0'
        Info: Total cell delay = 1.618 ns ( 21.65 % )
        Info: Total interconnect delay = 5.857 ns ( 78.35 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.681 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.070 ns) + CELL(0.548 ns) = 2.681 ns; Loc. = LCFF_X64_Y18_N17; Fanout = 1; REG Node = 'ledg~reg0'
        Info: Total cell delay = 1.493 ns ( 55.69 % )
        Info: Total interconnect delay = 1.188 ns ( 44.31 % )
Info: tco from clock "clk" to destination pin "ledg" through register "ledg~reg0" is 7.175 ns
    Info: + Longest clock path from clock "clk" to source register is 2.681 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.070 ns) + CELL(0.548 ns) = 2.681 ns; Loc. = LCFF_X64_Y18_N17; Fanout = 1; REG Node = 'ledg~reg0'
        Info: Total cell delay = 1.493 ns ( 55.69 % )
        Info: Total interconnect delay = 1.188 ns ( 44.31 % )
    Info: + Micro clock to output delay of source is 0.255 ns
    Info: + Longest register to pin delay is 4.239 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y18_N17; Fanout = 1; REG Node = 'ledg~reg0'
        Info: 2: + IC(1.701 ns) + CELL(2.538 ns) = 4.239 ns; Loc. = PIN_AE22; Fanout = 0; PIN Node = 'ledg'
        Info: Total cell delay = 2.538 ns ( 59.87 % )
        Info: Total interconnect delay = 1.701 ns ( 40.13 % )
Info: th for register "key[0]" (data pin = "keyin[0]", clock pin = "clk") is 0.998 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.681 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.070 ns) + CELL(0.548 ns) = 2.681 ns; Loc. = LCFF_X64_Y18_N15; Fanout = 1; REG Node = 'key[0]'
        Info: Total cell delay = 1.493 ns ( 55.69 % )
        Info: Total interconnect delay = 1.188 ns ( 44.31 % )
    Info: + Micro hold delay of destination is 0.170 ns
    Info: - Shortest pin to register delay is 1.853 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N25; Fanout = 2; PIN Node = 'keyin[0]'
        Info: 2: + IC(0.669 ns) + CELL(0.153 ns) = 1.767 ns; Loc. = LCCOMB_X64_Y18_N14; Fanout = 1; COMB Node = 'key[0]~40'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.853 ns; Loc. = LCFF_X64_Y18_N15; Fanout = 1; REG Node = 'key[0]'
        Info: Total cell delay = 1.184 ns ( 63.90 % )
        Info: Total interconnect delay = 0.669 ns ( 36.10 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jan 09 14:57:52 2008
    Info: Elapsed time: 00:00:00