lock.vhd

来自「以QuatusⅡ为平台」· VHDL 代码 · 共 59 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

entity lock is
port(
     clk:in std_logic;
     keyin:in std_logic_vector(7 downto 0);
     lockon: in std_logic;
     lockoff:in std_logic;
     keychange:in std_logic;
     reset:in std_logic;
     ledr:out std_logic;
     ledg:out std_logic
);
end lock;

architecture lock of lock is


begin
     process(reset,clk)
     variable lockflag:std_logic:='0';
     variable key:std_logic_vector(7 downto 0):="00000001";
     begin
        if reset='0'then
          key:="00000001";
          ledg<='1';
          ledr<='0';
          lockflag:='0';
        else
            if clk'event and clk='1' then
                 if lockon='0' then
                      if keyin=key or lockflag='1' then
                          ledg<='1';
                          ledr<='0';
                          lockflag:='1';
                          if keychange='0' then
                             key:=keyin;
                             ledg<='1';
                             ledr<='0';
                          end if;
                       else
                           ledg<='0';
                           ledr<='1';
                           lockflag:='0';
                       end if;
                  elsif lockoff='0' then
                        ledg<='0';
                        ledr<='1';
                        lockflag:='0';
                  else
                        ledg<=lockflag;
                        ledr<=not lockflag;
                  end if;         
             end if;
        end if;
    end process;
end lock;