lock.map.qmsg

以QuatusⅡ为平台

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Web Edition " "Info: Version 5.0 Build 148 04/26/2005 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 09 14:57:27 2008 " "Info: Processing started: Wed Jan 09 14:57:27 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lock -c lock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lock -c lock" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lock-lock " "Info: Found design unit 1: lock-lock" {  } { { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 18 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 lock " "Info: Found entity 1: lock" {  } { { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lock " "Info: Elaborating entity \"lock\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 14 -1 0 } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 24 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "36 " "Info: Implemented 36 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "13 " "Info: Implemented 13 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "21 " "Info: Implemented 21 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 09 14:57:29 2008 " "Info: Processing ended: Wed Jan 09 14:57:29 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}