flowled.sim.rpt

FPGA开发入门的Verilog HDL程序---流水灯,真实可用

; |flowled|lpm_add_sub:Add0|addcore:adder|_~43                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~43                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~44                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~44                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~50                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~50                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~51                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~51                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~52                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~52                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~53                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~53                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~54                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~54                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~55                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~55                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~56                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~56                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~57                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~57                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~58                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~58                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~59                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~59                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~60                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~60                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~61                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~61                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~62                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~62                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~63                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~63                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~64                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~64                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~65                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~65                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~66                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~66                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~67                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~67                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~73                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~73                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~74                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~74                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~75                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~75                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~76                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~76                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~77                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~77                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~78                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~78                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~79                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~79                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~80                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~80                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~81                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~81                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~82                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~82                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~83                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~83                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~84                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~84                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~85                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~85                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~86                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~86                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~87                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~87                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~88                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~88                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~89                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~89                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~90                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~90                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[23] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[23] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[22] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[22]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[22] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[22] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[21] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[21]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[21] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[21] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[20] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[20]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[20] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[20] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[19] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[19]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[19] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[19] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[18] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[18]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[18] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[18] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[17] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[17]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[17] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[17] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[16] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[16]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[16] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[16] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[15] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[15]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[15] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[15] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[14] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[14]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[14] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[14] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[13] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[13]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[13] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[13] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[12] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[12]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[12] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[12] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[11] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9]  ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9]       ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9]  ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]  ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8]  ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8]       ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8]  ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]  ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7]  ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7]       ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7]  ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]  ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6]  ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6]       ; cout             ;
+--------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                                                                    ;
+--------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------+
; Node Name                                                                ; Output Port Name                                                              ; Output Port Type ;
+--------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------+
; |flowled|led_r~0                                                         ; |flowled|led_r~0                                                              ; out              ;
; |flowled|led_r~1                                                         ; |flowled|led_r~1                                                              ; out              ;
; |flowled|led_r~2                                                         ; |flowled|led_r~2                                                              ; out              ;
; |flowled|led_r~3                                                         ; |flowled|led_r~3                                                              ; out              ;
; |flowled|led_r~4