flowled.sim.rpt

FPGA开发入门的Verilog HDL程序---流水灯,真实可用

; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[16]                   ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[16]                        ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[15]                   ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[15]                        ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[14]                   ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[14]                        ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[13]                   ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[13]                        ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[12]                   ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[12]                        ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[11]                   ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[11]                        ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[10]                   ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[10]                        ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[9]                    ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[9]                         ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[8]                    ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[8]                         ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[7]                    ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[7]                         ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[6]                    ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[6]                         ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[5]                    ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[5]                         ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[4]                    ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[4]                         ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[3]                    ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[3]                         ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[2]                    ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[2]                         ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[1]                    ; |flowled|lpm_add_sub:Add0|addcore:adder|datab_node[1]                         ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[23]~1             ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[23]~1                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[22]~2             ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[22]~2                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[21]~3             ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[21]~3                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[20]~4             ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[20]~4                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[19]~5             ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[19]~5                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[18]~6             ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[18]~6                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[17]~7             ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[17]~7                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[16]~8             ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[16]~8                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[15]~9             ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[15]~9                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[14]~10            ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[14]~10                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[13]~11            ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[13]~11                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[12]~12            ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[12]~12                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[11]~13            ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[11]~13                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[10]~14            ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[10]~14                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[9]~15             ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[9]~15                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[8]~16             ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[8]~16                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]~17             ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]~17                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[6]~18             ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[6]~18                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[23]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[23]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[22]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[22]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[21]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[21]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[20]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[20]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[19]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[19]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[18]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[18]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[17]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[17]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[16]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[16]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[15]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[15]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[14]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[14]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[13]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[13]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[12]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[12]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[11]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[11]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[10]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[10]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[9]                ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[9]                     ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[8]                ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[8]                     ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                     ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~4                              ; |flowled|lpm_add_sub:Add0|addcore:adder|_~4                                   ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~5                              ; |flowled|lpm_add_sub:Add0|addcore:adder|_~5                                   ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~6                              ; |flowled|lpm_add_sub:Add0|addcore:adder|_~6                                   ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~7                              ; |flowled|lpm_add_sub:Add0|addcore:adder|_~7                                   ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~8                              ; |flowled|lpm_add_sub:Add0|addcore:adder|_~8                                   ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~9                              ; |flowled|lpm_add_sub:Add0|addcore:adder|_~9                                   ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~10                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~10                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~11                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~11                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~12                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~12                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~13                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~13                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~14                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~14                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~15                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~15                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~16                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~16                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~17                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~17                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~18                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~18                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~19                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~19                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~20                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~20                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~21                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~21                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~22                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~22                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~23                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~23                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~24                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~24                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~25                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~25                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~26                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~26                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~27                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~27                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~28                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~28                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~29                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~29                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~30                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~30                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~31                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~31                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~32                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~32                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~33                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~33                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~34                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~34                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~35                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~35                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~36                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~36                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~37                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~37                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~38                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~38                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~39                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~39                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~40                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~40                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~41                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~41                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~42                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~42                                  ; out0             ;