flowled.sim.rpt

FPGA开发入门的Verilog HDL程序---流水灯,真实可用

+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      19.24 % ;
; Total nodes checked                                 ; 294          ;
; Total output ports checked                          ; 317          ;
; Total output ports with complete 1/0-value coverage ; 61           ;
; Total output ports with no 1/0-value coverage       ; 253          ;
; Total output ports with no 1-value coverage         ; 253          ;
; Total output ports with no 0-value coverage         ; 256          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                               ;
+-------------------------------------------------------------------------+------------------------------------------------------------------------------+------------------+
; Node Name                                                               ; Output Port Name                                                             ; Output Port Type ;
+-------------------------------------------------------------------------+------------------------------------------------------------------------------+------------------+
; |flowled|count~17                                                       ; |flowled|count~17                                                            ; out              ;
; |flowled|count~18                                                       ; |flowled|count~18                                                            ; out              ;
; |flowled|count~19                                                       ; |flowled|count~19                                                            ; out              ;
; |flowled|count~20                                                       ; |flowled|count~20                                                            ; out              ;
; |flowled|count~21                                                       ; |flowled|count~21                                                            ; out              ;
; |flowled|count~22                                                       ; |flowled|count~22                                                            ; out              ;
; |flowled|count~23                                                       ; |flowled|count~23                                                            ; out              ;
; |flowled|count[4]                                                       ; |flowled|count[4]                                                            ; out              ;
; |flowled|count[3]                                                       ; |flowled|count[3]                                                            ; out              ;
; |flowled|count[2]                                                       ; |flowled|count[2]                                                            ; out              ;
; |flowled|count[1]                                                       ; |flowled|count[1]                                                            ; out              ;
; |flowled|count[0]                                                       ; |flowled|count[0]                                                            ; out              ;
; |flowled|clk                                                            ; |flowled|clk                                                                 ; out              ;
; |flowled|lpm_add_sub:Add0|result_node[0]                                ; |flowled|lpm_add_sub:Add0|result_node[0]                                     ; out0             ;
; |flowled|lpm_add_sub:Add0|result_node[1]                                ; |flowled|lpm_add_sub:Add0|result_node[1]                                     ; out0             ;
; |flowled|lpm_add_sub:Add0|result_node[2]                                ; |flowled|lpm_add_sub:Add0|result_node[2]                                     ; out0             ;
; |flowled|lpm_add_sub:Add0|result_node[3]                                ; |flowled|lpm_add_sub:Add0|result_node[3]                                     ; out0             ;
; |flowled|lpm_add_sub:Add0|result_node[4]                                ; |flowled|lpm_add_sub:Add0|result_node[4]                                     ; out0             ;
; |flowled|lpm_add_sub:Add0|result_node[5]                                ; |flowled|lpm_add_sub:Add0|result_node[5]                                     ; out0             ;
; |flowled|lpm_add_sub:Add0|result_node[6]                                ; |flowled|lpm_add_sub:Add0|result_node[6]                                     ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0             ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~0                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~0                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~3                             ; |flowled|lpm_add_sub:Add0|addcore:adder|_~3                                  ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[4]~20            ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[4]~20                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~21            ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~21                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~22            ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~22                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~23            ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~23                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[6]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[6]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[5]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[5]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[4]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[4]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]               ; |flowled|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]                    ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~46                            ; |flowled|lpm_add_sub:Add0|addcore:adder|_~46                                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~47                            ; |flowled|lpm_add_sub:Add0|addcore:adder|_~47                                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~48                            ; |flowled|lpm_add_sub:Add0|addcore:adder|_~48                                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~49                            ; |flowled|lpm_add_sub:Add0|addcore:adder|_~49                                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~68                            ; |flowled|lpm_add_sub:Add0|addcore:adder|_~68                                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~69                            ; |flowled|lpm_add_sub:Add0|addcore:adder|_~69                                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~70                            ; |flowled|lpm_add_sub:Add0|addcore:adder|_~70                                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~71                            ; |flowled|lpm_add_sub:Add0|addcore:adder|_~71                                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~72                            ; |flowled|lpm_add_sub:Add0|addcore:adder|_~72                                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~91                            ; |flowled|lpm_add_sub:Add0|addcore:adder|_~91                                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~92                            ; |flowled|lpm_add_sub:Add0|addcore:adder|_~92                                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~93                            ; |flowled|lpm_add_sub:Add0|addcore:adder|_~93                                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~94                            ; |flowled|lpm_add_sub:Add0|addcore:adder|_~94                                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|_~95                            ; |flowled|lpm_add_sub:Add0|addcore:adder|_~95                                 ; out0             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; sout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0]      ; cout             ;
; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |flowled|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; sout             ;
+-------------------------------------------------------------------------+------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                    ;
+--------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------+
; Node Name                                                                ; Output Port Name                                                              ; Output Port Type ;
+--------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------------+
; |flowled|led_r~0                                                         ; |flowled|led_r~0                                                              ; out              ;