flowled.map.summary

FPGA开发入门的Verilog HDL程序---流水灯,真实可用

Analysis & Synthesis Status : Successful - Tue Jul 22 02:08:30 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : flowled
Top-level Entity Name : flowled
Family : Cyclone
Total logic elements : 67
Total pins : 9
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0