flowled.tan.rpt

FPGA开发入门的Verilog HDL程序---流水灯,真实可用

; N/A                                     ; 142.11 MHz ( period = 7.037 ns )                    ; count[5]  ; count[15] ; clk        ; clk      ; None                        ; None                      ; 6.776 ns                ;
; N/A                                     ; 142.17 MHz ( period = 7.034 ns )                    ; count[5]  ; count[10] ; clk        ; clk      ; None                        ; None                      ; 6.773 ns                ;
; N/A                                     ; 142.23 MHz ( period = 7.031 ns )                    ; count[5]  ; count[19] ; clk        ; clk      ; None                        ; None                      ; 6.770 ns                ;
; N/A                                     ; 142.25 MHz ( period = 7.030 ns )                    ; count[5]  ; count[17] ; clk        ; clk      ; None                        ; None                      ; 6.769 ns                ;
; N/A                                     ; 142.53 MHz ( period = 7.016 ns )                    ; count[6]  ; count[15] ; clk        ; clk      ; None                        ; None                      ; 6.755 ns                ;
; N/A                                     ; 142.59 MHz ( period = 7.013 ns )                    ; count[6]  ; count[10] ; clk        ; clk      ; None                        ; None                      ; 6.752 ns                ;
; N/A                                     ; 142.65 MHz ( period = 7.010 ns )                    ; count[6]  ; count[19] ; clk        ; clk      ; None                        ; None                      ; 6.749 ns                ;
; N/A                                     ; 142.67 MHz ( period = 7.009 ns )                    ; count[6]  ; count[17] ; clk        ; clk      ; None                        ; None                      ; 6.748 ns                ;
; N/A                                     ; 142.80 MHz ( period = 7.003 ns )                    ; count[0]  ; count[15] ; clk        ; clk      ; None                        ; None                      ; 6.742 ns                ;
; N/A                                     ; 142.86 MHz ( period = 7.000 ns )                    ; count[0]  ; count[10] ; clk        ; clk      ; None                        ; None                      ; 6.739 ns                ;
; N/A                                     ; 142.92 MHz ( period = 6.997 ns )                    ; count[0]  ; count[19] ; clk        ; clk      ; None                        ; None                      ; 6.736 ns                ;
; N/A                                     ; 142.94 MHz ( period = 6.996 ns )                    ; count[0]  ; count[17] ; clk        ; clk      ; None                        ; None                      ; 6.735 ns                ;
; N/A                                     ; 144.18 MHz ( period = 6.936 ns )                    ; count[8]  ; count[7]  ; clk        ; clk      ; None                        ; None                      ; 6.675 ns                ;
; N/A                                     ; 144.28 MHz ( period = 6.931 ns )                    ; count[8]  ; count[18] ; clk        ; clk      ; None                        ; None                      ; 6.670 ns                ;
; N/A                                     ; 144.49 MHz ( period = 6.921 ns )                    ; count[10] ; led_r[2]  ; clk        ; clk      ; None                        ; None                      ; 6.660 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;           ;           ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------+
; tco                                                                ;
+-------+--------------+------------+----------+--------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To     ; From Clock ;
+-------+--------------+------------+----------+--------+------------+
; N/A   ; None         ; 8.292 ns   ; led_r[2] ; led[2] ; clk        ;
; N/A   ; None         ; 8.202 ns   ; led_r[0] ; led[0] ; clk        ;
; N/A   ; None         ; 7.865 ns   ; led_r[1] ; led[1] ; clk        ;
; N/A   ; None         ; 7.836 ns   ; led_r[7] ; led[7] ; clk        ;
; N/A   ; None         ; 7.830 ns   ; led_r[3] ; led[3] ; clk        ;
; N/A   ; None         ; 7.829 ns   ; led_r[4] ; led[4] ; clk        ;
; N/A   ; None         ; 7.826 ns   ; led_r[5] ; led[5] ; clk        ;
; N/A   ; None         ; 7.824 ns   ; led_r[6] ; led[6] ; clk        ;
+-------+--------------+------------+----------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Jul 22 02:08:38 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off flowled -c flowled --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 118.08 MHz between source register "count[4]" and destination register "led_r[3]" (period= 8.469 ns)
    Info: + Longest register to register delay is 8.208 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y15_N2; Fanout = 3; REG Node = 'count[4]'
        Info: 2: + IC(1.242 ns) + CELL(0.423 ns) = 1.665 ns; Loc. = LC_X13_Y16_N7; Fanout = 2; COMB Node = 'Add0~368'
        Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.743 ns; Loc. = LC_X13_Y16_N8; Fanout = 2; COMB Node = 'Add0~370'
        Info: 4: + IC(0.000 ns) + CELL(0.271 ns) = 2.014 ns; Loc. = LC_X13_Y16_N9; Fanout = 6; COMB Node = 'Add0~372'
        Info: 5: + IC(0.000 ns) + CELL(0.136 ns) = 2.150 ns; Loc. = LC_X13_Y15_N4; Fanout = 6; COMB Node = 'Add0~380'
        Info: 6: + IC(0.000 ns) + CELL(0.208 ns) = 2.358 ns; Loc. = LC_X13_Y15_N9; Fanout = 6; COMB Node = 'Add0~396'
        Info: 7: + IC(0.000 ns) + CELL(0.679 ns) = 3.037 ns; Loc. = LC_X13_Y14_N0; Fanout = 2; COMB Node = 'Add0~389'
        Info: 8: + IC(1.220 ns) + CELL(0.442 ns) = 4.699 ns; Loc. = LC_X14_Y15_N4; Fanout = 8; COMB Node = 'Equal0~245'
        Info: 9: + IC(1.121 ns) + CELL(0.292 ns) = 6.112 ns; Loc. = LC_X12_Y15_N7; Fanout = 9; COMB Node = 'Equal0~247'
        Info: 10: + IC(1.229 ns) + CELL(0.867 ns) = 8.208 ns; Loc. = LC_X11_Y16_N4; Fanout = 3; REG Node = 'led_r[3]'
        Info: Total cell delay = 3.396 ns ( 41.37 % )
        Info: Total interconnect delay = 4.812 ns ( 58.63 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clk'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X11_Y16_N4; Fanout = 3; REG Node = 'led_r[3]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: - Longest clock path from clock "clk" to source register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clk'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X14_Y15_N2; Fanout = 3; REG Node = 'count[4]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "led[2]" through register "led_r[2]" is 8.292 ns
    Info: + Longest clock path from clock "clk" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X12_Y15_N6; Fanout = 3; REG Node = 'led_r[2]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.114 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y15_N6; Fanout = 3; REG Node = 'led_r[2]'
        Info: 2: + IC(2.990 ns) + CELL(2.124 ns) = 5.114 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'led[2]'
        Info: Total cell delay = 2.124 ns ( 41.53 % )
        Info: Total interconnect delay = 2.990 ns ( 58.47 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Jul 22 02:08:39 2008
    Info: Elapsed time: 00:00:01