ch_fir.hier_info

基于分布式算法的FPGA实现的FIR滤波器源码

address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT


|CH_FIR|input_process:inst
s[0] <= Serial_adder4:inst.S[0]
s[1] <= Serial_adder4:inst.S[1]
s[2] <= Serial_adder4:inst.S[2]
s[3] <= Serial_adder4:inst.S[3]
clk => Serial_adder4:inst.clk
clk => ptos:inst2.clk
clk => shiftregister:inst1.cp
clear => Serial_adder4:inst.clear
ptos_load => ptos:inst2.ptos_load
data[0] => ptos:inst2.data[0]
data[1] => ptos:inst2.data[1]
data[2] => ptos:inst2.data[2]
data[3] => ptos:inst2.data[3]
data[4] => ptos:inst2.data[4]
data[5] => ptos:inst2.data[5]
data[6] => ptos:inst2.data[6]
data[7] => ptos:inst2.data[7]


|CH_FIR|input_process:inst|Serial_adder4:inst
A[0] => serial_adder:label1:0:serial_adderx.A
A[1] => serial_adder:label1:1:serial_adderx.A
A[2] => serial_adder:label1:2:serial_adderx.A
A[3] => serial_adder:label1:3:serial_adderx.A
B[0] => serial_adder:label1:0:serial_adderx.B
B[1] => serial_adder:label1:1:serial_adderx.B
B[2] => serial_adder:label1:2:serial_adderx.B
B[3] => serial_adder:label1:3:serial_adderx.B
clk => serial_adder:label1:3:serial_adderx.clk
clk => serial_adder:label1:2:serial_adderx.clk
clk => serial_adder:label1:1:serial_adderx.clk
clk => serial_adder:label1:0:serial_adderx.clk
clear => serial_adder:label1:3:serial_adderx.clr
clear => serial_adder:label1:2:serial_adderx.clr
clear => serial_adder:label1:1:serial_adderx.clr
clear => serial_adder:label1:0:serial_adderx.clr
S[0] <= serial_adder:label1:0:serial_adderx.S
S[1] <= serial_adder:label1:1:serial_adderx.S
S[2] <= serial_adder:label1:2:serial_adderx.S
S[3] <= serial_adder:label1:3:serial_adderx.S


|CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:0:serial_adderx
A => temp1.IN0
A => Cout~0.IN0
B => temp1.IN1
B => Cout~0.IN1
clk => Cin.CLK
clr => Cin~0.OUTPUTSELECT
S <= S~0.DB_MAX_OUTPUT_PORT_TYPE


|CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:1:serial_adderx
A => temp1.IN0
A => Cout~0.IN0
B => temp1.IN1
B => Cout~0.IN1
clk => Cin.CLK
clr => Cin~0.OUTPUTSELECT
S <= S~0.DB_MAX_OUTPUT_PORT_TYPE


|CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:2:serial_adderx
A => temp1.IN0
A => Cout~0.IN0
B => temp1.IN1
B => Cout~0.IN1
clk => Cin.CLK
clr => Cin~0.OUTPUTSELECT
S <= S~0.DB_MAX_OUTPUT_PORT_TYPE


|CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:3:serial_adderx
A => temp1.IN0
A => Cout~0.IN0
B => temp1.IN1
B => Cout~0.IN1
clk => Cin.CLK
clr => Cin~0.OUTPUTSELECT
S <= S~0.DB_MAX_OUTPUT_PORT_TYPE


|CH_FIR|input_process:inst|shiftregister:inst1
din => shift_reg:label2:0:shift_regx.di
din => doutB[0].DATAIN
cp => shift_reg:label2:6:shift_regx.cp
cp => shift_reg:label2:5:shift_regx.cp
cp => shift_reg:label2:4:shift_regx.cp
cp => shift_reg:label2:3:shift_regx.cp
cp => shift_reg:label2:2:shift_regx.cp
cp => shift_reg:label2:1:shift_regx.cp
cp => shift_reg:label2:0:shift_regx.cp
doutA[0] <= shift_reg:label2:6:shift_regx.do
doutA[1] <= shift_reg:label2:5:shift_regx.do
doutA[2] <= shift_reg:label2:4:shift_regx.do
doutA[3] <= shift_reg:label2:3:shift_regx.do
doutB[0] <= din.DB_MAX_OUTPUT_PORT_TYPE
doutB[1] <= shift_reg:label2:0:shift_regx.do
doutB[2] <= shift_reg:label2:1:shift_regx.do
doutB[3] <= shift_reg:label2:2:shift_regx.do


|CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx
di => q[1].DATAIN
cp => q[1].CLK
cp => q[2].CLK
cp => q[3].CLK
cp => q[4].CLK
cp => q[5].CLK
cp => q[6].CLK
cp => q[7].CLK
cp => q[8].CLK
cp => do~reg0.CLK
do <= do~reg0.DB_MAX_OUTPUT_PORT_TYPE


|CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:1:shift_regx
di => q[1].DATAIN
cp => q[1].CLK
cp => q[2].CLK
cp => q[3].CLK
cp => q[4].CLK
cp => q[5].CLK
cp => q[6].CLK
cp => q[7].CLK
cp => q[8].CLK
cp => do~reg0.CLK
do <= do~reg0.DB_MAX_OUTPUT_PORT_TYPE


|CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx
di => q[1].DATAIN
cp => q[1].CLK
cp => q[2].CLK
cp => q[3].CLK
cp => q[4].CLK
cp => q[5].CLK
cp => q[6].CLK
cp => q[7].CLK
cp => q[8].CLK
cp => do~reg0.CLK
do <= do~reg0.DB_MAX_OUTPUT_PORT_TYPE


|CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx
di => q[1].DATAIN
cp => q[1].CLK
cp => q[2].CLK
cp => q[3].CLK
cp => q[4].CLK
cp => q[5].CLK
cp => q[6].CLK
cp => q[7].CLK
cp => q[8].CLK
cp => do~reg0.CLK
do <= do~reg0.DB_MAX_OUTPUT_PORT_TYPE


|CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx
di => q[1].DATAIN
cp => q[1].CLK
cp => q[2].CLK
cp => q[3].CLK
cp => q[4].CLK
cp => q[5].CLK
cp => q[6].CLK
cp => q[7].CLK
cp => q[8].CLK
cp => do~reg0.CLK
do <= do~reg0.DB_MAX_OUTPUT_PORT_TYPE


|CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx
di => q[1].DATAIN
cp => q[1].CLK
cp => q[2].CLK
cp => q[3].CLK
cp => q[4].CLK
cp => q[5].CLK
cp => q[6].CLK
cp => q[7].CLK
cp => q[8].CLK
cp => do~reg0.CLK
do <= do~reg0.DB_MAX_OUTPUT_PORT_TYPE


|CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:6:shift_regx
di => q[1].DATAIN
cp => q[1].CLK
cp => q[2].CLK
cp => q[3].CLK
cp => q[4].CLK
cp => q[5].CLK
cp => q[6].CLK
cp => q[7].CLK
cp => q[8].CLK
cp => do~reg0.CLK
do <= do~reg0.DB_MAX_OUTPUT_PORT_TYPE


|CH_FIR|input_process:inst|ptos:inst2
data[0] => q_temP~6.DATAB
data[1] => q_temP~5.DATAB
data[2] => q_temP~4.DATAB
data[3] => q_temP~3.DATAB
data[4] => q_temP~2.DATAB
data[5] => q_temP~1.DATAB
data[6] => q_temP~0.DATAB
data[7] => q_temP[7].DATAIN
clk => q_temP[0].CLK
clk => q_temP[1].CLK
clk => q_temP[2].CLK
clk => q_temP[3].CLK
clk => q_temP[4].CLK
clk => q_temP[5].CLK
clk => q_temP[6].CLK
clk => q_temP[7].CLK
ptos_load => q_temP~0.OUTPUTSELECT
ptos_load => q_temP~1.OUTPUTSELECT
ptos_load => q_temP~2.OUTPUTSELECT
ptos_load => q_temP~3.OUTPUTSELECT
ptos_load => q_temP~4.OUTPUTSELECT
ptos_load => q_temP~5.OUTPUTSELECT
ptos_load => q_temP~6.OUTPUTSELECT
ptos_load => q_temP[7].ENA
q <= q_temP[0].DB_MAX_OUTPUT_PORT_TYPE