ch_fir.hier_info

基于分布式算法的FPGA实现的FIR滤波器源码

|CH_FIR
Q[0] <= LATCH8:inst1.Q[0]
Q[1] <= LATCH8:inst1.Q[1]
Q[2] <= LATCH8:inst1.Q[2]
Q[3] <= LATCH8:inst1.Q[3]
Q[4] <= LATCH8:inst1.Q[4]
Q[5] <= LATCH8:inst1.Q[5]
Q[6] <= LATCH8:inst1.Q[6]
Q[7] <= LATCH8:inst1.Q[7]
Q[8] <= LATCH8:inst1.Q[8]
Q[9] <= LATCH8:inst1.Q[9]
Q[10] <= LATCH8:inst1.Q[10]
start => controller:inst3.start
clk => controller:inst3.clk
clk => LATCH8:inst1.CLK
clk => mac:inst2.clk
clk => input_process:inst.clk
data[0] => input_process:inst.data[0]
data[1] => input_process:inst.data[1]
data[2] => input_process:inst.data[2]
data[3] => input_process:inst.data[3]
data[4] => input_process:inst.data[4]
data[5] => input_process:inst.data[5]
data[6] => input_process:inst.data[6]
data[7] => input_process:inst.data[7]


|CH_FIR|LATCH8:inst1
D[0] => Q_TEMP[0].DATAIN
D[1] => Q_TEMP[1].DATAIN
D[2] => Q_TEMP[2].DATAIN
D[3] => Q_TEMP[3].DATAIN
D[4] => Q_TEMP[4].DATAIN
D[5] => Q_TEMP[5].DATAIN
D[6] => Q_TEMP[6].DATAIN
D[7] => Q_TEMP[7].DATAIN
D[8] => Q_TEMP[8].DATAIN
D[9] => Q_TEMP[9].DATAIN
D[10] => Q_TEMP[10].DATAIN
OE => Q_TEMP[0].ENA
OE => Q_TEMP[1].ENA
OE => Q_TEMP[2].ENA
OE => Q_TEMP[3].ENA
OE => Q_TEMP[4].ENA
OE => Q_TEMP[5].ENA
OE => Q_TEMP[6].ENA
OE => Q_TEMP[7].ENA
OE => Q_TEMP[8].ENA
OE => Q_TEMP[9].ENA
OE => Q_TEMP[10].ENA
CLK => Q_TEMP[0].CLK
CLK => Q_TEMP[1].CLK
CLK => Q_TEMP[2].CLK
CLK => Q_TEMP[3].CLK
CLK => Q_TEMP[4].CLK
CLK => Q_TEMP[5].CLK
CLK => Q_TEMP[6].CLK
CLK => Q_TEMP[7].CLK
CLK => Q_TEMP[8].CLK
CLK => Q_TEMP[9].CLK
CLK => Q_TEMP[10].CLK
Q[0] <= Q_TEMP[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Q_TEMP[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Q_TEMP[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q_TEMP[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Q_TEMP[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Q_TEMP[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= Q_TEMP[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= Q_TEMP[7].DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= Q_TEMP[8].DB_MAX_OUTPUT_PORT_TYPE
Q[9] <= Q_TEMP[9].DB_MAX_OUTPUT_PORT_TYPE
Q[10] <= Q_TEMP[10].DB_MAX_OUTPUT_PORT_TYPE


|CH_FIR|controller:inst3
clr <= cc:inst.clr
start => cc:inst.start
clk => cc:inst.clk
clk => div9:inst1.clk
plsr_load <= cc:inst.plsr_load
latch_result <= cc:inst.latch_result
clear <= cc:inst.clear


|CH_FIR|controller:inst3|cc:inst
start => Selector0.IN3
start => next_state.s0.DATAB
clk => present_state~0.IN1
z => next_state.s3.DATAB
z => Selector1.IN2
clear <= clear~0.DB_MAX_OUTPUT_PORT_TYPE
clr <= clear~0.DB_MAX_OUTPUT_PORT_TYPE
plsr_load <= present_state.s1.DB_MAX_OUTPUT_PORT_TYPE
latch_result <= present_state.s3.DB_MAX_OUTPUT_PORT_TYPE


|CH_FIR|controller:inst3|div9:inst1
clk => cnt[0].CLK
clk => cnt[1].CLK
clk => cnt[2].CLK
clk => cnt[3].CLK
clk => clk_temp.CLK
div9 <= clk_temp.DB_MAX_OUTPUT_PORT_TYPE


|CH_FIR|mac:inst2
sa_out[0] <= sa:inst.sa_out[0]
sa_out[1] <= sa:inst.sa_out[1]
sa_out[2] <= sa:inst.sa_out[2]
sa_out[3] <= sa:inst.sa_out[3]
sa_out[4] <= sa:inst.sa_out[4]
sa_out[5] <= sa:inst.sa_out[5]
sa_out[6] <= sa:inst.sa_out[6]
sa_out[7] <= sa:inst.sa_out[7]
sa_out[8] <= sa:inst.sa_out[8]
sa_out[9] <= sa:inst.sa_out[9]
sa_out[10] <= sa:inst.sa_out[10]
clk => sa:inst.clk
clk => rom:inst1.clock
clr => sa:inst.clr
address[0] => rom:inst1.address[0]
address[1] => rom:inst1.address[1]
address[2] => rom:inst1.address[2]
address[3] => rom:inst1.address[3]


|CH_FIR|mac:inst2|sa:inst
sa_in[0] => Add0.IN11
sa_in[1] => Add0.IN10
sa_in[2] => Add0.IN9
sa_in[3] => Add0.IN8
sa_in[4] => Add0.IN7
sa_in[5] => Add0.IN6
sa_in[6] => Add0.IN5
sa_in[7] => Add0.IN4
sa_in[8] => Add0.IN3
sa_in[9] => Add0.IN1
sa_in[9] => Add0.IN2
sa_out[0] <= sa_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sa_out[1] <= sa_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sa_out[2] <= sa_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sa_out[3] <= sa_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sa_out[4] <= sa_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sa_out[5] <= sa_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sa_out[6] <= sa_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sa_out[7] <= sa_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sa_out[8] <= sa_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sa_out[9] <= sa_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sa_out[10] <= sa_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk => sa_out[0]~reg0.CLK
clk => sa_out[1]~reg0.CLK
clk => sa_out[2]~reg0.CLK
clk => sa_out[3]~reg0.CLK
clk => sa_out[4]~reg0.CLK
clk => sa_out[5]~reg0.CLK
clk => sa_out[6]~reg0.CLK
clk => sa_out[7]~reg0.CLK
clk => sa_out[8]~reg0.CLK
clk => sa_out[9]~reg0.CLK
clk => sa_out[10]~reg0.CLK
clk => shift_out[0].CLK
clk => shift_out[1].CLK
clk => shift_out[2].CLK
clk => shift_out[3].CLK
clk => shift_out[4].CLK
clk => shift_out[5].CLK
clk => shift_out[6].CLK
clk => shift_out[7].CLK
clk => shift_out[8].CLK
clk => shift_out[9].CLK
clr => shift_out~0.OUTPUTSELECT
clr => shift_out~1.OUTPUTSELECT
clr => shift_out~2.OUTPUTSELECT
clr => shift_out~3.OUTPUTSELECT
clr => shift_out~4.OUTPUTSELECT
clr => shift_out~5.OUTPUTSELECT
clr => shift_out~6.OUTPUTSELECT
clr => shift_out~7.OUTPUTSELECT
clr => shift_out~8.OUTPUTSELECT
clr => shift_out~9.OUTPUTSELECT
clr => sa_out[3]~reg0.ENA
clr => sa_out[2]~reg0.ENA
clr => sa_out[1]~reg0.ENA
clr => sa_out[0]~reg0.ENA
clr => sa_out[4]~reg0.ENA
clr => sa_out[5]~reg0.ENA
clr => sa_out[6]~reg0.ENA
clr => sa_out[7]~reg0.ENA
clr => sa_out[8]~reg0.ENA
clr => sa_out[9]~reg0.ENA
clr => sa_out[10]~reg0.ENA


|CH_FIR|mac:inst2|rom:inst1
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]


|CH_FIR|mac:inst2|rom:inst1|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_jp61:auto_generated.address_a[0]
address_a[1] => altsyncram_jp61:auto_generated.address_a[1]
address_a[2] => altsyncram_jp61:auto_generated.address_a[2]
address_a[3] => altsyncram_jp61:auto_generated.address_a[3]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_jp61:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_jp61:auto_generated.q_a[0]
q_a[1] <= altsyncram_jp61:auto_generated.q_a[1]
q_a[2] <= altsyncram_jp61:auto_generated.q_a[2]
q_a[3] <= altsyncram_jp61:auto_generated.q_a[3]
q_a[4] <= altsyncram_jp61:auto_generated.q_a[4]
q_a[5] <= altsyncram_jp61:auto_generated.q_a[5]
q_a[6] <= altsyncram_jp61:auto_generated.q_a[6]
q_a[7] <= altsyncram_jp61:auto_generated.q_a[7]
q_a[8] <= altsyncram_jp61:auto_generated.q_a[8]
q_a[9] <= altsyncram_jp61:auto_generated.q_a[9]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|CH_FIR|mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1