ch_fir.fit.qmsg

基于分布式算法的FPGA实现的FIR滤波器源码

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.785 ns memory register " "Info: Estimated most critical path is memory to register delay of 3.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.109 ns) 0.109 ns mac:inst2\|rom:inst1\|altsyncram:altsyncram_component\|altsyncram_jp61:auto_generated\|q_a\[0\] 1 MEM M4K_X11_Y9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X11_Y9; Fanout = 2; MEM Node = 'mac:inst2\|rom:inst1\|altsyncram:altsyncram_component\|altsyncram_jp61:auto_generated\|q_a\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_jp61.tdf" "" { Text "D:/altera/70/quartus/CH_FIR/db/altsyncram_jp61.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.621 ns) 1.586 ns mac:inst2\|sa:inst\|Add0~133 2 COMB LAB_X12_Y9 2 " "Info: 2: + IC(0.856 ns) + CELL(0.621 ns) = 1.586 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~133'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.477 ns" { mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] mac:inst2|sa:inst|Add0~133 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.672 ns mac:inst2\|sa:inst\|Add0~135 3 COMB LAB_X12_Y9 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.672 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~135'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { mac:inst2|sa:inst|Add0~133 mac:inst2|sa:inst|Add0~135 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.758 ns mac:inst2\|sa:inst\|Add0~137 4 COMB LAB_X12_Y9 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.758 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~137'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { mac:inst2|sa:inst|Add0~135 mac:inst2|sa:inst|Add0~137 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.844 ns mac:inst2\|sa:inst\|Add0~139 5 COMB LAB_X12_Y9 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.844 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~139'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { mac:inst2|sa:inst|Add0~137 mac:inst2|sa:inst|Add0~139 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.930 ns mac:inst2\|sa:inst\|Add0~141 6 COMB LAB_X12_Y9 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.930 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~141'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { mac:inst2|sa:inst|Add0~139 mac:inst2|sa:inst|Add0~141 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.016 ns mac:inst2\|sa:inst\|Add0~143 7 COMB LAB_X12_Y9 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 2.016 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~143'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { mac:inst2|sa:inst|Add0~141 mac:inst2|sa:inst|Add0~143 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.102 ns mac:inst2\|sa:inst\|Add0~145 8 COMB LAB_X12_Y9 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 2.102 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~145'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { mac:inst2|sa:inst|Add0~143 mac:inst2|sa:inst|Add0~145 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.188 ns mac:inst2\|sa:inst\|Add0~147 9 COMB LAB_X12_Y9 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.188 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~147'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { mac:inst2|sa:inst|Add0~145 mac:inst2|sa:inst|Add0~147 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.274 ns mac:inst2\|sa:inst\|Add0~149 10 COMB LAB_X12_Y9 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.274 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~149'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { mac:inst2|sa:inst|Add0~147 mac:inst2|sa:inst|Add0~149 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.360 ns mac:inst2\|sa:inst\|Add0~151 11 COMB LAB_X12_Y9 1 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.360 ns; Loc. = LAB_X12_Y9; Fanout = 1; COMB Node = 'mac:inst2\|sa:inst\|Add0~151'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { mac:inst2|sa:inst|Add0~149 mac:inst2|sa:inst|Add0~151 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 2.866 ns mac:inst2\|sa:inst\|Add0~152 12 COMB LAB_X12_Y9 2 " "Info: 12: + IC(0.000 ns) + CELL(0.506 ns) = 2.866 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~152'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { mac:inst2|sa:inst|Add0~151 mac:inst2|sa:inst|Add0~152 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.370 ns) 3.677 ns mac:inst2\|sa:inst\|shift_out~172 13 COMB LAB_X12_Y9 1 " "Info: 13: + IC(0.441 ns) + CELL(0.370 ns) = 3.677 ns; Loc. = LAB_X12_Y9; Fanout = 1; COMB Node = 'mac:inst2\|sa:inst\|shift_out~172'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { mac:inst2|sa:inst|Add0~152 mac:inst2|sa:inst|shift_out~172 } "NODE_NAME" } } { "../work11/sa.vhd" "" { Text "D:/altera/70/quartus/work11/sa.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.785 ns mac:inst2\|sa:inst\|shift_out\[9\] 14 REG LAB_X12_Y9 3 " "Info: 14: + IC(0.000 ns) + CELL(0.108 ns) = 3.785 ns; Loc. = LAB_X12_Y9; Fanout = 3; REG Node = 'mac:inst2\|sa:inst\|shift_out\[9\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { mac:inst2|sa:inst|shift_out~172 mac:inst2|sa:inst|shift_out[9] } "NODE_NAME" } } { "../work11/sa.vhd" "" { Text "D:/altera/70/quartus/work11/sa.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.488 ns ( 65.73 % ) " "Info: Total cell delay = 2.488 ns ( 65.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.297 ns ( 34.27 % ) " "Info: Total interconnect delay = 1.297 ns ( 34.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.785 ns" { mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] mac:inst2|sa:inst|Add0~133 mac:inst2|sa:inst|Add0~135 mac:inst2|sa:inst|Add0~137 mac:inst2|sa:inst|Add0~139 mac:inst2|sa:inst|Add0~141 mac:inst2|sa:inst|Add0~143 mac:inst2|sa:inst|Add0~145 mac:inst2|sa:inst|Add0~147 mac:inst2|sa:inst|Add0~149 mac:inst2|sa:inst|Add0~151 mac:inst2|sa:inst|Add0~152 mac:inst2|sa:inst|shift_out~172 mac:inst2|sa:inst|shift_out[9] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X11_Y0 X22_Y9 " "Info: The peak interconnect region extends from location X11_Y0 to location X22_Y9" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "11 " "Warning: Found 11 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[10\] 0 " "Info: Pin \"Q\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[9\] 0 " "Info: Pin \"Q\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[8\] 0 " "Info: Pin \"Q\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[7\] 0 " "Info: Pin \"Q\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[6\] 0 " "Info: Pin \"Q\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[5\] 0 " "Info: Pin \"Q\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[4\] 0 " "Info: Pin \"Q\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[3\] 0 " "Info: Pin \"Q\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[2\] 0 " "Info: Pin \"Q\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[1\] 0 " "Info: Pin \"Q\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q\[0\] 0 " "Info: Pin \"Q\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "174 " "Info: Allocated 174 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 03 11:51:43 2008 " "Info: Processing ended: Thu Jul 03 11:51:43 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/altera/70/quartus/CH_FIR/CH_FIR.fit.smsg " "Info: Generated suppressed messages file D:/altera/70/quartus/CH_FIR/CH_FIR.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}