📄 ch_fir.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory mac:inst2\|rom:inst1\|altsyncram:altsyncram_component\|altsyncram_jp61:auto_generated\|q_a\[0\] register mac:inst2\|sa:inst\|shift_out\[4\] 241.49 MHz 4.141 ns Internal " "Info: Clock \"clk\" has Internal fmax of 241.49 MHz between source memory \"mac:inst2\|rom:inst1\|altsyncram:altsyncram_component\|altsyncram_jp61:auto_generated\|q_a\[0\]\" and destination register \"mac:inst2\|sa:inst\|shift_out\[4\]\" (period= 4.141 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.854 ns + Longest memory register " "Info: + Longest memory to register delay is 3.854 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.109 ns) 0.109 ns mac:inst2\|rom:inst1\|altsyncram:altsyncram_component\|altsyncram_jp61:auto_generated\|q_a\[0\] 1 MEM M4K_X11_Y9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X11_Y9; Fanout = 2; MEM Node = 'mac:inst2\|rom:inst1\|altsyncram:altsyncram_component\|altsyncram_jp61:auto_generated\|q_a\[0\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_jp61.tdf" "" { Text "D:/altera/70/quartus/CH_FIR/db/altsyncram_jp61.tdf" 40 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.052 ns) + CELL(0.596 ns) 1.757 ns mac:inst2\|sa:inst\|Add0~133 2 COMB LCCOMB_X12_Y9_N10 2 " "Info: 2: + IC(1.052 ns) + CELL(0.596 ns) = 1.757 ns; Loc. = LCCOMB_X12_Y9_N10; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~133'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.648 ns" { mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] mac:inst2|sa:inst|Add0~133 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.843 ns mac:inst2\|sa:inst\|Add0~135 3 COMB LCCOMB_X12_Y9_N12 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.843 ns; Loc. = LCCOMB_X12_Y9_N12; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~135'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { mac:inst2|sa:inst|Add0~133 mac:inst2|sa:inst|Add0~135 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 2.033 ns mac:inst2\|sa:inst\|Add0~137 4 COMB LCCOMB_X12_Y9_N14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.190 ns) = 2.033 ns; Loc. = LCCOMB_X12_Y9_N14; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~137'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { mac:inst2|sa:inst|Add0~135 mac:inst2|sa:inst|Add0~137 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.119 ns mac:inst2\|sa:inst\|Add0~139 5 COMB LCCOMB_X12_Y9_N16 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 2.119 ns; Loc. = LCCOMB_X12_Y9_N16; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~139'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { mac:inst2|sa:inst|Add0~137 mac:inst2|sa:inst|Add0~139 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.205 ns mac:inst2\|sa:inst\|Add0~141 6 COMB LCCOMB_X12_Y9_N18 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 2.205 ns; Loc. = LCCOMB_X12_Y9_N18; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~141'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { mac:inst2|sa:inst|Add0~139 mac:inst2|sa:inst|Add0~141 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 2.711 ns mac:inst2\|sa:inst\|Add0~142 7 COMB LCCOMB_X12_Y9_N20 2 " "Info: 7: + IC(0.000 ns) + CELL(0.506 ns) = 2.711 ns; Loc. = LCCOMB_X12_Y9_N20; Fanout = 2; COMB Node = 'mac:inst2\|sa:inst\|Add0~142'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { mac:inst2|sa:inst|Add0~141 mac:inst2|sa:inst|Add0~142 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.665 ns) + CELL(0.370 ns) 3.746 ns mac:inst2\|sa:inst\|shift_out~177 8 COMB LCCOMB_X13_Y9_N16 1 " "Info: 8: + IC(0.665 ns) + CELL(0.370 ns) = 3.746 ns; Loc. = LCCOMB_X13_Y9_N16; Fanout = 1; COMB Node = 'mac:inst2\|sa:inst\|shift_out~177'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.035 ns" { mac:inst2|sa:inst|Add0~142 mac:inst2|sa:inst|shift_out~177 } "NODE_NAME" } } { "../work11/sa.vhd" "" { Text "D:/altera/70/quartus/work11/sa.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.854 ns mac:inst2\|sa:inst\|shift_out\[4\] 9 REG LCFF_X13_Y9_N17 2 " "Info: 9: + IC(0.000 ns) + CELL(0.108 ns) = 3.854 ns; Loc. = LCFF_X13_Y9_N17; Fanout = 2; REG Node = 'mac:inst2\|sa:inst\|shift_out\[4\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { mac:inst2|sa:inst|shift_out~177 mac:inst2|sa:inst|shift_out[4] } "NODE_NAME" } } { "../work11/sa.vhd" "" { Text "D:/altera/70/quartus/work11/sa.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.137 ns ( 55.45 % ) " "Info: Total cell delay = 2.137 ns ( 55.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.717 ns ( 44.55 % ) " "Info: Total interconnect delay = 1.717 ns ( 44.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.854 ns" { mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] mac:inst2|sa:inst|Add0~133 mac:inst2|sa:inst|Add0~135 mac:inst2|sa:inst|Add0~137 mac:inst2|sa:inst|Add0~139 mac:inst2|sa:inst|Add0~141 mac:inst2|sa:inst|Add0~142 mac:inst2|sa:inst|shift_out~177 mac:inst2|sa:inst|shift_out[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.854 ns" { mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] mac:inst2|sa:inst|Add0~133 mac:inst2|sa:inst|Add0~135 mac:inst2|sa:inst|Add0~137 mac:inst2|sa:inst|Add0~139 mac:inst2|sa:inst|Add0~141 mac:inst2|sa:inst|Add0~142 mac:inst2|sa:inst|shift_out~177 mac:inst2|sa:inst|shift_out[4] } { 0.000ns 1.052ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.665ns 0.000ns } { 0.109ns 0.596ns 0.086ns 0.190ns 0.086ns 0.086ns 0.506ns 0.370ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.067 ns - Smallest " "Info: - Smallest clock skew is -0.067 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.783 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.783 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CH_FIR.bdf" "" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 600 128 296 616 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 130 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 130; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "CH_FIR.bdf" "" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 600 128 296 616 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.888 ns) + CELL(0.666 ns) 2.783 ns mac:inst2\|sa:inst\|shift_out\[4\] 3 REG LCFF_X13_Y9_N17 2 " "Info: 3: + IC(0.888 ns) + CELL(0.666 ns) = 2.783 ns; Loc. = LCFF_X13_Y9_N17; Fanout = 2; REG Node = 'mac:inst2\|sa:inst\|shift_out\[4\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.554 ns" { clk~clkctrl mac:inst2|sa:inst|shift_out[4] } "NODE_NAME" } } { "../work11/sa.vhd" "" { Text "D:/altera/70/quartus/work11/sa.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.10 % ) " "Info: Total cell delay = 1.756 ns ( 63.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.027 ns ( 36.90 % ) " "Info: Total interconnect delay = 1.027 ns ( 36.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.783 ns" { clk clk~clkctrl mac:inst2|sa:inst|shift_out[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.783 ns" { clk clk~combout clk~clkctrl mac:inst2|sa:inst|shift_out[4] } { 0.000ns 0.000ns 0.139ns 0.888ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.850 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.850 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CH_FIR.bdf" "" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 600 128 296 616 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 130 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 130; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "CH_FIR.bdf" "" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 600 128 296 616 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.815 ns) 2.850 ns mac:inst2\|rom:inst1\|altsyncram:altsyncram_component\|altsyncram_jp61:auto_generated\|q_a\[0\] 3 MEM M4K_X11_Y9 2 " "Info: 3: + IC(0.806 ns) + CELL(0.815 ns) = 2.850 ns; Loc. = M4K_X11_Y9; Fanout = 2; MEM Node = 'mac:inst2\|rom:inst1\|altsyncram:altsyncram_component\|altsyncram_jp61:auto_generated\|q_a\[0\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.621 ns" { clk~clkctrl mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_jp61.tdf" "" { Text "D:/altera/70/quartus/CH_FIR/db/altsyncram_jp61.tdf" 40 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.905 ns ( 66.84 % ) " "Info: Total cell delay = 1.905 ns ( 66.84 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.945 ns ( 33.16 % ) " "Info: Total interconnect delay = 0.945 ns ( 33.16 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.850 ns" { clk clk~clkctrl mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.850 ns" { clk clk~combout clk~clkctrl mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.139ns 0.806ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.783 ns" { clk clk~clkctrl mac:inst2|sa:inst|shift_out[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.783 ns" { clk clk~combout clk~clkctrl mac:inst2|sa:inst|shift_out[4] } { 0.000ns 0.000ns 0.139ns 0.888ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.850 ns" { clk clk~clkctrl mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.850 ns" { clk clk~combout clk~clkctrl mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.139ns 0.806ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" { } { { "db/altsyncram_jp61.tdf" "" { Text "D:/altera/70/quartus/CH_FIR/db/altsyncram_jp61.tdf" 40 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "../work11/sa.vhd" "" { Text "D:/altera/70/quartus/work11/sa.vhd" 19 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.854 ns" { mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] mac:inst2|sa:inst|Add0~133 mac:inst2|sa:inst|Add0~135 mac:inst2|sa:inst|Add0~137 mac:inst2|sa:inst|Add0~139 mac:inst2|sa:inst|Add0~141 mac:inst2|sa:inst|Add0~142 mac:inst2|sa:inst|shift_out~177 mac:inst2|sa:inst|shift_out[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.854 ns" { mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] mac:inst2|sa:inst|Add0~133 mac:inst2|sa:inst|Add0~135 mac:inst2|sa:inst|Add0~137 mac:inst2|sa:inst|Add0~139 mac:inst2|sa:inst|Add0~141 mac:inst2|sa:inst|Add0~142 mac:inst2|sa:inst|shift_out~177 mac:inst2|sa:inst|shift_out[4] } { 0.000ns 1.052ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.665ns 0.000ns } { 0.109ns 0.596ns 0.086ns 0.190ns 0.086ns 0.086ns 0.506ns 0.370ns 0.108ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.783 ns" { clk clk~clkctrl mac:inst2|sa:inst|shift_out[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.783 ns" { clk clk~combout clk~clkctrl mac:inst2|sa:inst|shift_out[4] } { 0.000ns 0.000ns 0.139ns 0.888ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.850 ns" { clk clk~clkctrl mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.850 ns" { clk clk~combout clk~clkctrl mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.139ns 0.806ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "controller:inst3\|cc:inst\|present_state.s0 start clk 5.181 ns register " "Info: tsu for register \"controller:inst3\|cc:inst\|present_state.s0\" (data pin = \"start\", clock pin = \"clk\") is 5.181 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.004 ns + Longest pin register " "Info: + Longest pin to register delay is 8.004 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns start 1 PIN PIN_53 2 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_53; Fanout = 2; PIN Node = 'start'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "CH_FIR.bdf" "" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 552 120 288 568 "start" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.311 ns) + CELL(0.651 ns) 7.896 ns controller:inst3\|cc:inst\|present_state.s0~42 2 COMB LCCOMB_X13_Y9_N10 1 " "Info: 2: + IC(6.311 ns) + CELL(0.651 ns) = 7.896 ns; Loc. = LCCOMB_X13_Y9_N10; Fanout = 1; COMB Node = 'controller:inst3\|cc:inst\|present_state.s0~42'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.962 ns" { start controller:inst3|cc:inst|present_state.s0~42 } "NODE_NAME" } } { "../controller/cc.vhd" "" { Text "D:/altera/70/quartus/controller/cc.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.004 ns controller:inst3\|cc:inst\|present_state.s0 3 REG LCFF_X13_Y9_N11 13 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.004 ns; Loc. = LCFF_X13_Y9_N11; Fanout = 13; REG Node = 'controller:inst3\|cc:inst\|present_state.s0'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { controller:inst3|cc:inst|present_state.s0~42 controller:inst3|cc:inst|present_state.s0 } "NODE_NAME" } } { "../controller/cc.vhd" "" { Text "D:/altera/70/quartus/controller/cc.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.693 ns ( 21.15 % ) " "Info: Total cell delay = 1.693 ns ( 21.15 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.311 ns ( 78.85 % ) " "Info: Total interconnect delay = 6.311 ns ( 78.85 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.004 ns" { start controller:inst3|cc:inst|present_state.s0~42 controller:inst3|cc:inst|present_state.s0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.004 ns" { start start~combout controller:inst3|cc:inst|present_state.s0~42 controller:inst3|cc:inst|present_state.s0 } { 0.000ns 0.000ns 6.311ns 0.000ns } { 0.000ns 0.934ns 0.651ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "../controller/cc.vhd" "" { Text "D:/altera/70/quartus/controller/cc.vhd" 9 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.783 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.783 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CH_FIR.bdf" "" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 600 128 296 616 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 130 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 130; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "CH_FIR.bdf" "" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 600 128 296 616 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.888 ns) + CELL(0.666 ns) 2.783 ns controller:inst3\|cc:inst\|present_state.s0 3 REG LCFF_X13_Y9_N11 13 " "Info: 3: + IC(0.888 ns) + CELL(0.666 ns) = 2.783 ns; Loc. = LCFF_X13_Y9_N11; Fanout = 13; REG Node = 'controller:inst3\|cc:inst\|present_state.s0'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.554 ns" { clk~clkctrl controller:inst3|cc:inst|present_state.s0 } "NODE_NAME" } } { "../controller/cc.vhd" "" { Text "D:/altera/70/quartus/controller/cc.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.10 % ) " "Info: Total cell delay = 1.756 ns ( 63.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.027 ns ( 36.90 % ) " "Info: Total interconnect delay = 1.027 ns ( 36.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.783 ns" { clk clk~clkctrl controller:inst3|cc:inst|present_state.s0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.783 ns" { clk clk~combout clk~clkctrl controller:inst3|cc:inst|present_state.s0 } { 0.000ns 0.000ns 0.139ns 0.888ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.004 ns" { start controller:inst3|cc:inst|present_state.s0~42 controller:inst3|cc:inst|present_state.s0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.004 ns" { start start~combout controller:inst3|cc:inst|present_state.s0~42 controller:inst3|cc:inst|present_state.s0 } { 0.000ns 0.000ns 6.311ns 0.000ns } { 0.000ns 0.934ns 0.651ns 0.108ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.783 ns" { clk clk~clkctrl controller:inst3|cc:inst|present_state.s0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.783 ns" { clk clk~combout clk~clkctrl controller:inst3|cc:inst|present_state.s0 } { 0.000ns 0.000ns 0.139ns 0.888ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Q\[7\] LATCH8:inst1\|Q_TEMP\[7\] 8.892 ns register " "Info: tco from clock \"clk\" to destination pin \"Q\[7\]\" through register \"LATCH8:inst1\|Q_TEMP\[7\]\" is 8.892 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.774 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CH_FIR.bdf" "" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 600 128 296 616 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 130 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 130; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "CH_FIR.bdf" "" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 600 128 296 616 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.666 ns) 2.774 ns LATCH8:inst1\|Q_TEMP\[7\] 3 REG LCFF_X10_Y9_N13 1 " "Info: 3: + IC(0.879 ns) + CELL(0.666 ns) = 2.774 ns; Loc. = LCFF_X10_Y9_N13; Fanout = 1; REG Node = 'LATCH8:inst1\|Q_TEMP\[7\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.545 ns" { clk~clkctrl LATCH8:inst1|Q_TEMP[7] } "NODE_NAME" } } { "../LATCH8/LATCH8.vhd" "" { Text "D:/altera/70/quartus/LATCH8/LATCH8.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.30 % ) " "Info: Total cell delay = 1.756 ns ( 63.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 36.70 % ) " "Info: Total interconnect delay = 1.018 ns ( 36.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl LATCH8:inst1|Q_TEMP[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { clk clk~combout clk~clkctrl LATCH8:inst1|Q_TEMP[7] } { 0.000ns 0.000ns 0.139ns 0.879ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "../LATCH8/LATCH8.vhd" "" { Text "D:/altera/70/quartus/LATCH8/LATCH8.vhd" 15 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.814 ns + Longest register pin " "Info: + Longest register to pin delay is 5.814 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LATCH8:inst1\|Q_TEMP\[7\] 1 REG LCFF_X10_Y9_N13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y9_N13; Fanout = 1; REG Node = 'LATCH8:inst1\|Q_TEMP\[7\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { LATCH8:inst1|Q_TEMP[7] } "NODE_NAME" } } { "../LATCH8/LATCH8.vhd" "" { Text "D:/altera/70/quartus/LATCH8/LATCH8.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.584 ns) + CELL(3.230 ns) 5.814 ns Q\[7\] 2 PIN PIN_31 0 " "Info: 2: + IC(2.584 ns) + CELL(3.230 ns) = 5.814 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'Q\[7\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.814 ns" { LATCH8:inst1|Q_TEMP[7] Q[7] } "NODE_NAME" } } { "CH_FIR.bdf" "" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 560 992 1168 576 "Q\[10..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.230 ns ( 55.56 % ) " "Info: Total cell delay = 3.230 ns ( 55.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.584 ns ( 44.44 % ) " "Info: Total interconnect delay = 2.584 ns ( 44.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.814 ns" { LATCH8:inst1|Q_TEMP[7] Q[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.814 ns" { LATCH8:inst1|Q_TEMP[7] Q[7] } { 0.000ns 2.584ns } { 0.000ns 3.230ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl LATCH8:inst1|Q_TEMP[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { clk clk~combout clk~clkctrl LATCH8:inst1|Q_TEMP[7] } { 0.000ns 0.000ns 0.139ns 0.879ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.814 ns" { LATCH8:inst1|Q_TEMP[7] Q[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.814 ns" { LATCH8:inst1|Q_TEMP[7] Q[7] } { 0.000ns 2.584ns } { 0.000ns 3.230ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "input_process:inst\|ptos:inst2\|q_temP\[6\] data\[6\] clk 0.350 ns register " "Info: th for register \"input_process:inst\|ptos:inst2\|q_temP\[6\]\" (data pin = \"data\[6\]\", clock pin = \"clk\") is 0.350 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.776 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.776 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CH_FIR.bdf" "" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 600 128 296 616 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 130 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 130; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "CH_FIR.bdf" "" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 600 128 296 616 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.881 ns) + CELL(0.666 ns) 2.776 ns input_process:inst\|ptos:inst2\|q_temP\[6\] 3 REG LCFF_X30_Y9_N23 1 " "Info: 3: + IC(0.881 ns) + CELL(0.666 ns) = 2.776 ns; Loc. = LCFF_X30_Y9_N23; Fanout = 1; REG Node = 'input_process:inst\|ptos:inst2\|q_temP\[6\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.547 ns" { clk~clkctrl input_process:inst|ptos:inst2|q_temP[6] } "NODE_NAME" } } { "../ptos.vhd" "" { Text "D:/altera/70/quartus/ptos.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.26 % ) " "Info: Total cell delay = 1.756 ns ( 63.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.020 ns ( 36.74 % ) " "Info: Total interconnect delay = 1.020 ns ( 36.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.776 ns" { clk clk~clkctrl input_process:inst|ptos:inst2|q_temP[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.776 ns" { clk clk~combout clk~clkctrl input_process:inst|ptos:inst2|q_temP[6] } { 0.000ns 0.000ns 0.139ns 0.881ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "../ptos.vhd" "" { Text "D:/altera/70/quartus/ptos.vhd" 14 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.732 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns data\[6\] 1 PIN PIN_90 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_90; Fanout = 1; PIN Node = 'data\[6\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[6] } "NODE_NAME" } } { "CH_FIR.bdf" "" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 368 176 344 384 "data\[7..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.318 ns) + CELL(0.206 ns) 2.624 ns input_process:inst\|ptos:inst2\|q_temP~111 2 COMB LCCOMB_X30_Y9_N22 1 " "Info: 2: + IC(1.318 ns) + CELL(0.206 ns) = 2.624 ns; Loc. = LCCOMB_X30_Y9_N22; Fanout = 1; COMB Node = 'input_process:inst\|ptos:inst2\|q_temP~111'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.524 ns" { data[6] input_process:inst|ptos:inst2|q_temP~111 } "NODE_NAME" } } { "../ptos.vhd" "" { Text "D:/altera/70/quartus/ptos.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.732 ns input_process:inst\|ptos:inst2\|q_temP\[6\] 3 REG LCFF_X30_Y9_N23 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.732 ns; Loc. = LCFF_X30_Y9_N23; Fanout = 1; REG Node = 'input_process:inst\|ptos:inst2\|q_temP\[6\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { input_process:inst|ptos:inst2|q_temP~111 input_process:inst|ptos:inst2|q_temP[6] } "NODE_NAME" } } { "../ptos.vhd" "" { Text "D:/altera/70/quartus/ptos.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.414 ns ( 51.76 % ) " "Info: Total cell delay = 1.414 ns ( 51.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.318 ns ( 48.24 % ) " "Info: Total interconnect delay = 1.318 ns ( 48.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.732 ns" { data[6] input_process:inst|ptos:inst2|q_temP~111 input_process:inst|ptos:inst2|q_temP[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.732 ns" { data[6] data[6]~combout input_process:inst|ptos:inst2|q_temP~111 input_process:inst|ptos:inst2|q_temP[6] } { 0.000ns 0.000ns 1.318ns 0.000ns } { 0.000ns 1.100ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.776 ns" { clk clk~clkctrl input_process:inst|ptos:inst2|q_temP[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.776 ns" { clk clk~combout clk~clkctrl input_process:inst|ptos:inst2|q_temP[6] } { 0.000ns 0.000ns 0.139ns 0.881ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.732 ns" { data[6] input_process:inst|ptos:inst2|q_temP~111 input_process:inst|ptos:inst2|q_temP[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.732 ns" { data[6] data[6]~combout input_process:inst|ptos:inst2|q_temP~111 input_process:inst|ptos:inst2|q_temP[6] } { 0.000ns 0.000ns 1.318ns 0.000ns } { 0.000ns 1.100ns 0.206ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -