ch_fir.fnsim.qmsg

基于分布式算法的FPGA实现的FIR滤波器源码

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cc controller:inst3\|cc:inst " "Info: Elaborating entity \"cc\" for hierarchy \"controller:inst3\|cc:inst\"" {  } { { "../controller/controller.bdf" "inst" { Schematic "D:/altera/70/quartus/controller/controller.bdf" { { 56 376 512 184 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div9 controller:inst3\|div9:inst1 " "Info: Elaborating entity \"div9\" for hierarchy \"controller:inst3\|div9:inst1\"" {  } { { "../controller/controller.bdf" "inst1" { Schematic "D:/altera/70/quartus/controller/controller.bdf" { { 88 232 328 184 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mac mac:inst2 " "Info: Elaborating entity \"mac\" for hierarchy \"mac:inst2\"" {  } { { "CH_FIR.bdf" "inst2" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 360 600 800 456 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sa mac:inst2\|sa:inst " "Info: Elaborating entity \"sa\" for hierarchy \"mac:inst2\|sa:inst\"" {  } { { "../mac/mac.bdf" "inst" { Schematic "D:/altera/70/quartus/mac/mac.bdf" { { 96 384 552 192 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom mac:inst2\|rom:inst1 " "Info: Elaborating entity \"rom\" for hierarchy \"mac:inst2\|rom:inst1\"" {  } { { "../mac/mac.bdf" "inst1" { Schematic "D:/altera/70/quartus/mac/mac.bdf" { { 96 176 328 192 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altsyncram.tdf" 434 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram mac:inst2\|rom:inst1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"mac:inst2\|rom:inst1\|altsyncram:altsyncram_component\"" {  } { { "../mac/rom.vhd" "altsyncram_component" { Text "D:/altera/70/quartus/mac/rom.vhd" 84 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "mac:inst2\|rom:inst1\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"mac:inst2\|rom:inst1\|altsyncram:altsyncram_component\"" {  } { { "../mac/rom.vhd" "" { Text "D:/altera/70/quartus/mac/rom.vhd" 84 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_jp61.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_jp61.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_jp61 " "Info: Found entity 1: altsyncram_jp61" {  } { { "db/altsyncram_jp61.tdf" "" { Text "D:/altera/70/quartus/CH_FIR/db/altsyncram_jp61.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_jp61 mac:inst2\|rom:inst1\|altsyncram:altsyncram_component\|altsyncram_jp61:auto_generated " "Info: Elaborating entity \"altsyncram_jp61\" for hierarchy \"mac:inst2\|rom:inst1\|altsyncram:altsyncram_component\|altsyncram_jp61:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/70/quartus/libraries/megafunctions/altsyncram.tdf" 917 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "input_process input_process:inst " "Info: Elaborating entity \"input_process\" for hierarchy \"input_process:inst\"" {  } { { "CH_FIR.bdf" "inst" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 344 368 512 472 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Serial_adder4.vhd 2 1 " "Warning: Using design file Serial_adder4.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Serial_adder4-structure " "Info: Found design unit 1: Serial_adder4-structure" {  } { { "Serial_adder4.vhd" "" { Text "D:/altera/70/quartus/CH_FIR/Serial_adder4.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Serial_adder4 " "Info: Found entity 1: Serial_adder4" {  } { { "Serial_adder4.vhd" "" { Text "D:/altera/70/quartus/CH_FIR/Serial_adder4.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Serial_adder4 input_process:inst\|Serial_adder4:inst " "Info: Elaborating entity \"Serial_adder4\" for hierarchy \"input_process:inst\|Serial_adder4:inst\"" {  } { { "../input_process/input_process.bdf" "inst" { Schematic "D:/altera/70/quartus/input_process/input_process.bdf" { { 192 736 856 320 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "serial_adder input_process:inst\|Serial_adder4:inst\|serial_adder:\\label1:0:serial_adderx " "Info: Elaborating entity \"serial_adder\" for hierarchy \"input_process:inst\|Serial_adder4:inst\|serial_adder:\\label1:0:serial_adderx\"" {  } { { "Serial_adder4.vhd" "\\label1:0:serial_adderx" { Text "D:/altera/70/quartus/CH_FIR/Serial_adder4.vhd" 20 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shiftregister input_process:inst\|shiftregister:inst1 " "Info: Elaborating entity \"shiftregister\" for hierarchy \"input_process:inst\|shiftregister:inst1\"" {  } { { "../input_process/input_process.bdf" "inst1" { Schematic "D:/altera/70/quartus/input_process/input_process.bdf" { { 192 512 632 288 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_reg input_process:inst\|shiftregister:inst1\|shift_reg:\\label2:0:shift_regx " "Info: Elaborating entity \"shift_reg\" for hierarchy \"input_process:inst\|shiftregister:inst1\|shift_reg:\\label2:0:shift_regx\"" {  } { { "../shiftregister/shiftregister.vhd" "\\label2:0:shift_regx" { Text "D:/altera/70/quartus/shiftregister/shiftregister.vhd" 20 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ptos input_process:inst\|ptos:inst2 " "Info: Elaborating entity \"ptos\" for hierarchy \"input_process:inst\|ptos:inst2\"" {  } { { "../input_process/input_process.bdf" "inst2" { Schematic "D:/altera/70/quartus/input_process/input_process.bdf" { { 192 384 480 288 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q_temP ptos.vhd(20) " "Warning (10492): VHDL Process Statement warning at ptos.vhd(20): signal \"q_temP\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../ptos.vhd" "" { Text "D:/altera/70/quartus/ptos.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 3 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 04 23:26:00 2008 " "Info: Processing ended: Fri Jul 04 23:26:00 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}