ch_fir.fnsim.qmsg

基于分布式算法的FPGA实现的FIR滤波器源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 04 23:25:58 2008 " "Info: Processing started: Fri Jul 04 23:25:58 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CH_FIR -c CH_FIR --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CH_FIR -c CH_FIR --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../mac/mac.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../mac/mac.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 mac " "Info: Found entity 1: mac" {  } { { "../mac/mac.bdf" "" { Schematic "D:/altera/70/quartus/mac/mac.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../controller/controller.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../controller/controller.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 controller " "Info: Found entity 1: controller" {  } { { "../controller/controller.bdf" "" { Schematic "D:/altera/70/quartus/controller/controller.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../input_process/input_process.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../input_process/input_process.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 input_process " "Info: Found entity 1: input_process" {  } { { "../input_process/input_process.bdf" "" { Schematic "D:/altera/70/quartus/input_process/input_process.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../ptos.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../ptos.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ptos-rtl " "Info: Found design unit 1: ptos-rtl" {  } { { "../ptos.vhd" "" { Text "D:/altera/70/quartus/ptos.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ptos " "Info: Found entity 1: ptos" {  } { { "../ptos.vhd" "" { Text "D:/altera/70/quartus/ptos.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../work11/sa.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../work11/sa.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sa-one " "Info: Found design unit 1: sa-one" {  } { { "../work11/sa.vhd" "" { Text "D:/altera/70/quartus/work11/sa.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sa " "Info: Found entity 1: sa" {  } { { "../work11/sa.vhd" "" { Text "D:/altera/70/quartus/work11/sa.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../shiftregister/shiftregister.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../shiftregister/shiftregister.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shiftregister-structure " "Info: Found design unit 1: shiftregister-structure" {  } { { "../shiftregister/shiftregister.vhd" "" { Text "D:/altera/70/quartus/shiftregister/shiftregister.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 shiftregister " "Info: Found entity 1: shiftregister" {  } { { "../shiftregister/shiftregister.vhd" "" { Text "D:/altera/70/quartus/shiftregister/shiftregister.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../serial_adder/serial_adde4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../serial_adder/serial_adde4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 serial_adder8-structure " "Info: Found design unit 1: serial_adder8-structure" {  } { { "../serial_adder/serial_adde4.vhd" "" { Text "D:/altera/70/quartus/serial_adder/serial_adde4.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Serial_adder8 " "Info: Found entity 1: Serial_adder8" {  } { { "../serial_adder/serial_adde4.vhd" "" { Text "D:/altera/70/quartus/serial_adder/serial_adde4.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../serial_adder/serial_adder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../serial_adder/serial_adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 serial_adder-structure " "Info: Found design unit 1: serial_adder-structure" {  } { { "../serial_adder/serial_adder.vhd" "" { Text "D:/altera/70/quartus/serial_adder/serial_adder.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 serial_adder " "Info: Found entity 1: serial_adder" {  } { { "../serial_adder/serial_adder.vhd" "" { Text "D:/altera/70/quartus/serial_adder/serial_adder.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../LATCH8/LATCH8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../LATCH8/LATCH8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LATCH8-ONE " "Info: Found design unit 1: LATCH8-ONE" {  } { { "../LATCH8/LATCH8.vhd" "" { Text "D:/altera/70/quartus/LATCH8/LATCH8.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 LATCH8 " "Info: Found entity 1: LATCH8" {  } { { "../LATCH8/LATCH8.vhd" "" { Text "D:/altera/70/quartus/LATCH8/LATCH8.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../mac/rom.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../mac/rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom-SYN " "Info: Found design unit 1: rom-SYN" {  } { { "../mac/rom.vhd" "" { Text "D:/altera/70/quartus/mac/rom.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rom " "Info: Found entity 1: rom" {  } { { "../mac/rom.vhd" "" { Text "D:/altera/70/quartus/mac/rom.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../FIR/shift_reg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../FIR/shift_reg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shift_reg-structure " "Info: Found design unit 1: shift_reg-structure" {  } { { "../FIR/shift_reg.vhd" "" { Text "D:/altera/70/quartus/FIR/shift_reg.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 shift_reg " "Info: Found entity 1: shift_reg" {  } { { "../FIR/shift_reg.vhd" "" { Text "D:/altera/70/quartus/FIR/shift_reg.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../div9/div9.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../div9/div9.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div9-one " "Info: Found design unit 1: div9-one" {  } { { "../div9/div9.vhd" "" { Text "D:/altera/70/quartus/div9/div9.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div9 " "Info: Found entity 1: div9" {  } { { "../div9/div9.vhd" "" { Text "D:/altera/70/quartus/div9/div9.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../controller/cc.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../controller/cc.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cc-cc_state " "Info: Found design unit 1: cc-cc_state" {  } { { "../controller/cc.vhd" "" { Text "D:/altera/70/quartus/controller/cc.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cc " "Info: Found entity 1: cc" {  } { { "../controller/cc.vhd" "" { Text "D:/altera/70/quartus/controller/cc.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CH_FIR.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file CH_FIR.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CH_FIR " "Info: Found entity 1: CH_FIR" {  } { { "CH_FIR.bdf" "" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "CH_FIR " "Info: Elaborating entity \"CH_FIR\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LATCH8 LATCH8:inst1 " "Info: Elaborating entity \"LATCH8\" for hierarchy \"LATCH8:inst1\"" {  } { { "CH_FIR.bdf" "inst1" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 536 832 968 632 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Q_TEMP LATCH8.vhd(20) " "Warning (10492): VHDL Process Statement warning at LATCH8.vhd(20): signal \"Q_TEMP\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../LATCH8/LATCH8.vhd" "" { Text "D:/altera/70/quartus/LATCH8/LATCH8.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "controller controller:inst3 " "Info: Elaborating entity \"controller\" for hierarchy \"controller:inst3\"" {  } { { "CH_FIR.bdf" "inst3" { Schematic "D:/altera/70/quartus/CH_FIR/CH_FIR.bdf" { { 528 352 496 656 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}