ch_fir.fit.summary

基于分布式算法的FPGA实现的FIR滤波器源码

Fitter Status : Successful - Thu Jul 03 11:51:43 2008
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : CH_FIR
Top-level Entity Name : CH_FIR
Family : Cyclone II
Device : EP2C8T144C8
Timing Models : Final
Total logic elements : 117 / 8,256 ( 1 % )
    Total combinational functions : 47 / 8,256 ( < 1 % )
    Dedicated logic registers : 116 / 8,256 ( 1 % )
Total registers : 116
Total pins : 21 / 85 ( 25 % )
Total virtual pins : 0
Total memory bits : 160 / 165,888 ( < 1 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )