ch_fir.tan.rpt

基于分布式算法的FPGA实现的FIR滤波器源码

+------------------------------+-------+---------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 5.181 ns                                       ; start                                                                                                              ; controller:inst3|cc:inst|present_state.s0                                                 ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 8.892 ns                                       ; LATCH8:inst1|Q_TEMP[7]                                                                                             ; Q[7]                                                                                      ; clk        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 0.350 ns                                       ; data[6]                                                                                                            ; input_process:inst|ptos:inst2|q_temP[6]                                                   ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|ram_block1a0~porta_address_reg3 ; mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[9] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                                                                    ;                                                                                           ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C8T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+