ch_fir.map.summary

基于分布式算法的FPGA实现的FIR滤波器源码

Analysis & Synthesis Status : Successful - Thu Jul 03 11:51:36 2008
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : CH_FIR
Top-level Entity Name : CH_FIR
Family : Cyclone II
Total logic elements : 116
    Total combinational functions : 47
    Dedicated logic registers : 116
Total registers : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total memory bits : N/A until Partition Merge
Embedded Multiplier 9-bit elements : N/A until Partition Merge
Total PLLs : N/A until Partition Merge