ch_fir.fit.smsg

基于分布式算法的FPGA实现的FIR滤波器源码

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Jul 03 11:51:39 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off CH_FIR -c CH_FIR
Info: Selected device EP2C8T144C8 for design "CH_FIR"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 194 of 194 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: No exact pin location assignment(s) for 21 pins of 21 total pins
    Info: Pin Q[10] not assigned to an exact location on the device
    Info: Pin Q[9] not assigned to an exact location on the device
    Info: Pin Q[8] not assigned to an exact location on the device
    Info: Pin Q[7] not assigned to an exact location on the device
    Info: Pin Q[6] not assigned to an exact location on the device
    Info: Pin Q[5] not assigned to an exact location on the device
    Info: Pin Q[4] not assigned to an exact location on the device
    Info: Pin Q[3] not assigned to an exact location on the device
    Info: Pin Q[2] not assigned to an exact location on the device
    Info: Pin Q[1] not assigned to an exact location on the device
    Info: Pin Q[0] not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin start not assigned to an exact location on the device
    Info: Pin data[0] not assigned to an exact location on the device
    Info: Pin data[1] not assigned to an exact location on the device
    Info: Pin data[2] not assigned to an exact location on the device
    Info: Pin data[3] not assigned to an exact location on the device
    Info: Pin data[4] not assigned to an exact location on the device
    Info: Pin data[5] not assigned to an exact location on the device
    Info: Pin data[6] not assigned to an exact location on the device
    Info: Pin data[7] not assigned to an exact location on the device
Info: Automatically promoted node clk (placed in PIN 17 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 20 (unused VREF, 3.30 VCCIO, 9 input, 11 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  14 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  20 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is memory to register delay of 3.785 ns
    Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X11_Y9; Fanout = 2; MEM Node = 'mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated|q_a[0]'
    Info: 2: + IC(0.856 ns) + CELL(0.621 ns) = 1.586 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2|sa:inst|Add0~133'
    Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.672 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2|sa:inst|Add0~135'
    Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.758 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2|sa:inst|Add0~137'
    Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.844 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2|sa:inst|Add0~139'
    Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.930 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2|sa:inst|Add0~141'
    Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 2.016 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2|sa:inst|Add0~143'
    Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 2.102 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2|sa:inst|Add0~145'
    Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.188 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2|sa:inst|Add0~147'
    Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.274 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2|sa:inst|Add0~149'
    Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.360 ns; Loc. = LAB_X12_Y9; Fanout = 1; COMB Node = 'mac:inst2|sa:inst|Add0~151'
    Info: 12: + IC(0.000 ns) + CELL(0.506 ns) = 2.866 ns; Loc. = LAB_X12_Y9; Fanout = 2; COMB Node = 'mac:inst2|sa:inst|Add0~152'
    Info: 13: + IC(0.441 ns) + CELL(0.370 ns) = 3.677 ns; Loc. = LAB_X12_Y9; Fanout = 1; COMB Node = 'mac:inst2|sa:inst|shift_out~172'
    Info: 14: + IC(0.000 ns) + CELL(0.108 ns) = 3.785 ns; Loc. = LAB_X12_Y9; Fanout = 3; REG Node = 'mac:inst2|sa:inst|shift_out[9]'
    Info: Total cell delay = 2.488 ns ( 65.73 % )
    Info: Total interconnect delay = 1.297 ns ( 34.27 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X11_Y0 to location X22_Y9
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 11 output pins without output pin load capacitance assignment
    Info: Pin "Q[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 174 megabytes of memory during processing
    Info: Processing ended: Thu Jul 03 11:51:43 2008
    Info: Elapsed time: 00:00:04