ch_fir.map.rpt

基于分布式算法的FPGA实现的FIR滤波器源码

; OUTDATA_REG_A                      ; CLOCK0               ; Untyped                              ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                              ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                              ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                              ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                              ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                              ;
; WIDTH_B                            ; 1                    ; Untyped                              ;
; WIDTHAD_B                          ; 1                    ; Untyped                              ;
; NUMWORDS_B                         ; 1                    ; Untyped                              ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                              ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                              ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                              ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                              ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                              ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                              ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                              ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                              ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                              ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                              ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                              ;
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer                       ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                              ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                              ;
; BYTE_SIZE                          ; 8                    ; Untyped                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                              ;
; INIT_FILE                          ; rom.mif              ; Untyped                              ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                              ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                              ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                              ;
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS               ; Untyped                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                              ;
; ENABLE_ECC                         ; FALSE                ; Untyped                              ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                              ;
; CBXI_PARAMETER                     ; altsyncram_jp61      ; Untyped                              ;
+------------------------------------+----------------------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Jul 03 11:51:32 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CH_FIR -c CH_FIR
Info: Found 1 design units, including 1 entities, in source file ../mac/mac.bdf
    Info: Found entity 1: mac
Info: Found 1 design units, including 1 entities, in source file ../controller/controller.bdf
    Info: Found entity 1: controller
Info: Found 1 design units, including 1 entities, in source file ../input_process/input_process.bdf
    Info: Found entity 1: input_process
Info: Found 2 design units, including 1 entities, in source file ../ptos.vhd
    Info: Found design unit 1: ptos-rtl
    Info: Found entity 1: ptos
Info: Found 2 design units, including 1 entities, in source file ../work11/sa.vhd
    Info: Found design unit 1: sa-one
    Info: Found entity 1: sa
Info: Found 2 design units, including 1 entities, in source file ../shiftregister/shiftregister.vhd
    Info: Found design unit 1: shiftregister-structure
    Info: Found entity 1: shiftregister
Info: Found 2 design units, including 1 entities, in source file ../serial_adder/serial_adde4.vhd
    Info: Found design unit 1: serial_adder8-structure
    Info: Found entity 1: Serial_adder8
Info: Found 2 design units, including 1 entities, in source file ../serial_adder/serial_adder.vhd
    Info: Found design unit 1: serial_adder-structure
    Info: Found entity 1: serial_adder
Info: Found 2 design units, including 1 entities, in source file ../LATCH8/LATCH8.vhd
    Info: Found design unit 1: LATCH8-ONE
    Info: Found entity 1: LATCH8
Info: Found 2 design units, including 1 entities, in source file ../mac/rom.vhd
    Info: Found design unit 1: rom-SYN
    Info: Found entity 1: rom
Info: Found 2 design units, including 1 entities, in source file ../FIR/shift_reg.vhd
    Info: Found design unit 1: shift_reg-structure
    Info: Found entity 1: shift_reg
Info: Found 2 design units, including 1 entities, in source file ../div9/div9.vhd
    Info: Found design unit 1: div9-one
    Info: Found entity 1: div9
Info: Found 2 design units, including 1 entities, in source file ../controller/cc.vhd
    Info: Found design unit 1: cc-cc_state
    Info: Found entity 1: cc
Info: Found 1 design units, including 1 entities, in source file CH_FIR.bdf
    Info: Found entity 1: CH_FIR
Info: Elaborating entity "CH_FIR" for the top level hierarchy
Info: Elaborating entity "LATCH8" for hierarchy "LATCH8:inst1"
Warning (10492): VHDL Process Statement warning at LATCH8.vhd(20): signal "Q_TEMP" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "controller" for hierarchy "controller:inst3"
Info: Elaborating entity "cc" for hierarchy "controller:inst3|cc:inst"
Info: Elaborating entity "div9" for hierarchy "controller:inst3|div9:inst1"
Info: Elaborating entity "mac" for hierarchy "mac:inst2"
Info: Elaborating entity "sa" for hierarchy "mac:inst2|sa:inst"
Info: Elaborating entity "rom" for hierarchy "mac:inst2|rom:inst1"
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "mac:inst2|rom:inst1|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "mac:inst2|rom:inst1|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_jp61.tdf
    Info: Found entity 1: altsyncram_jp61
Info: Elaborating entity "altsyncram_jp61" for hierarchy "mac:inst2|rom:inst1|altsyncram:altsyncram_component|altsyncram_jp61:auto_generated"
Info: Elaborating entity "input_process" for hierarchy "input_process:inst"
Warning: Using design file Serial_adder4.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: Serial_adder4-structure
    Info: Found entity 1: Serial_adder4
Info: Elaborating entity "Serial_adder4" for hierarchy "input_process:inst|Serial_adder4:inst"
Info: Elaborating entity "serial_adder" for hierarchy "input_process:inst|Serial_adder4:inst|serial_adder:\label1:0:serial_adderx"
Info: Elaborating entity "shiftregister" for hierarchy "input_process:inst|shiftregister:inst1"
Info: Elaborating entity "shift_reg" for hierarchy "input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx"
Info: Elaborating entity "ptos" for hierarchy "input_process:inst|ptos:inst2"
Warning (10492): VHDL Process Statement warning at ptos.vhd(20): signal "q_temP" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: State machine "|CH_FIR|controller:inst3|cc:inst|present_state" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|CH_FIR|controller:inst3|cc:inst|present_state"
Info: Encoding result for state machine "|CH_FIR|controller:inst3|cc:inst|present_state"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "controller:inst3|cc:inst|present_state.s3"
        Info: Encoded state bit "controller:inst3|cc:inst|present_state.s2"
        Info: Encoded state bit "controller:inst3|cc:inst|present_state.s1"
        Info: Encoded state bit "controller:inst3|cc:inst|present_state.s0"
    Info: State "|CH_FIR|controller:inst3|cc:inst|present_state.s0" uses code string "0000"
    Info: State "|CH_FIR|controller:inst3|cc:inst|present_state.s1" uses code string "0011"
    Info: State "|CH_FIR|controller:inst3|cc:inst|present_state.s2" uses code string "0101"
    Info: State "|CH_FIR|controller:inst3|cc:inst|present_state.s3" uses code string "1001"
Info: Implemented 162 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 11 output pins
    Info: Implemented 131 logic cells
    Info: Implemented 10 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 145 megabytes of memory during processing
    Info: Processing ended: Thu Jul 03 11:51:36 2008
    Info: Elapsed time: 00:00:04