serial_adde4.vhd

基于分布式算法的FPGA实现的FIR滤波器源码

Library ieee;
use ieee.Std_logic_1164.all;
entity Serial_adder8 is
Port(A:in std_logic_vector(3 downto 0);
B:in std_logic_vector(3 downto 0);
clk:in std_logic;
clear:in std_logic;
S:out std_logic_vector(7 downto 0));
end serial_adder8;
architecture structure of serial_adder8 is
component serial_adder
Port(A:in std_logic;
B:in std_logic;
clk:in std_logic;
clr:in std_logic;
S:out std_logic);
end component;
begin
label1:for i in 0 to 3 generate
serial_adderx:serial_adder port map(A(i),B(i),clk,clear,s(i));
end generate label1;
end structure;