xianshi.fit

使用vriloge硬件描述语言设计数字频率计

-- MAX+plus II Compiler Fit File      
-- Version 10.2 07/10/2002            
-- Compiled: 06/14/2008 16:39:39      

-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "xianshi"
BEGIN

    DEVICE = "EP1K10TC100-1";

    "COM0"                         : INPUT_PIN  = 91     ;
    "COM1"                         : INPUT_PIN  = 38     ;
    "COM2"                         : INPUT_PIN  = 89     ;
    "COM3"                         : INPUT_PIN  = 40     ;
    "a"                            : OUTPUT_PIN = 15     ;
    "b"                            : OUTPUT_PIN = 64     ;
    "c"                            : OUTPUT_PIN = 63     ;
    "d"                            : OUTPUT_PIN = 62     ;
    "e"                            : OUTPUT_PIN = 13     ;
    "f"                            : OUTPUT_PIN = 14     ;
    "g"                            : OUTPUT_PIN = 61     ;
    ":160"                         : LOCATION   = LC5_B5 ;
    ":182"                         : LOCATION   = LC2_B5 ;
    ":204"                         : LOCATION   = LC4_B5 ;
    ":226"                         : LOCATION   = LC6_B5 ;
    ":248"                         : LOCATION   = LC1_B5 ;
    ":270"                         : LOCATION   = LC3_B5 ;
    ":292"                         : LOCATION   = LC8_B5 ;

END;

INTERNAL_INFO "xianshi"
BEGIN
	DEVICE = EP1K10TC100-1;
    OD0P91  : LORAX = "1:FB0|2:FH0R1,PA0R1C4->LC5_B5,->LC2_B5,->LC4_B5,->LC6_B5,->LC1_B5,->LC3_B5,->LC8_B5||";
    OD2P38  : LORAX = "1:FB2|2:FH2R1,PA6R1C4->LC5_B5,->LC2_B5,->LC4_B5,->LC6_B5,->LC1_B5,->LC3_B5,->LC8_B5||";
    OD1P89  : LORAX = "1:FB1|2:FH1R1,PA20R1C4->LC5_B5,->LC2_B5,->LC4_B5,->LC6_B5,->LC1_B5,->LC3_B5,->LC8_B5||";
    OD3P40  : LORAX = "1:FB3|2:FH3R1,PA5R1C4->LC5_B5,->LC2_B5,->LC4_B5,->LC6_B5,->LC1_B5,->LC3_B5,->LC8_B5||";
    LC5_B5  : LORAX = "1:MSW4R1C5,G77R1->OH4R1P15|";
    LC2_B5  : LORAX = "1:MSW1R1C5,HHL16R1->OH9R1P64|";
    LC4_B5  : LORAX = "1:MSW3R1C5,G1R1->OH11R1P63|";
    LC6_B5  : LORAX = "1:MSW5R1C5,HHL39R1->OH13R1P62|";
    LC1_B5  : LORAX = "1:MSW0R1C5,G43R1->OH0R1P13|";
    LC3_B5  : LORAX = "1:MSW2R1C4,G13R1->OH2R1P14|";
    LC8_B5  : LORAX = "1:MSW7R1C5,HHL47R1->OH15R1P61|";
	LC5_B5  : LORAX2 = "OD2P38, OD3P40, OD0P91, OD1P89";
	LC2_B5  : LORAX2 = "OD2P38, OD0P91, OD1P89, OD3P40";
	LC4_B5  : LORAX2 = "OD2P38, OD3P40, OD1P89, OD0P91";
	LC6_B5  : LORAX2 = "OD2P38, OD3P40, OD0P91, OD1P89";
	LC1_B5  : LORAX2 = "OD2P38, OD3P40, OD0P91, OD1P89";
	LC3_B5  : LORAX2 = "OD2P38, OD3P40, OD1P89, OD0P91";
	LC8_B5  : LORAX2 = "OD2P38, OD3P40, OD1P89, OD0P91";
END;