buffter.v

来自「使用vriloge硬件描述语言设计数字频率计」· Verilog 代码 · 共 18 行

module buffer(A,B,C,D,E,F,G,H,clkbuf,BF0,BF1,BF2,BF3,BF4,BF5,BF6,BF7);
input[3:0]A,B,C,D,E,F,G,H;
input clkbuf;
output[3:0]BF0,BF1,BF2,BF3,BF4,BF5,BF6,BF7;
reg[3:0]BF0,BF1,BF2,BF3,BF4,BF5,BF6,BF7;
always @ (negedge clkbuf)
      begin
           BF0<=A;
           BF1<=B;
           BF2<=C;
           BF3<=D;
           BF4<=E;
           BF5<=F;
           BF6<=G;
           BF7<=H;
       end
endmodule