buffer.v

来自「使用vriloge硬件描述语言设计数字频率计」· Verilog 代码 · 共 86 行

module buffer(A,B,C,D,E,F,G,H,clkbuf,BF0,BF1,BF2,BF3,BF4,BF5,BF6,BF7);
input[3:0]A,B,C,D,E,F,G,H;
input clkbuf;
output[3:0]BF0,BF1,BF2,BF3,BF4,BF5,BF6,BF7;
reg[3:0]BF0,BF1,BF2,BF3,BF4,BF5,BF6,BF7;
always @ (negedge clkbuf)
      begin
         BF0<=A;
      if(H==0)
           begin
             BF7<=10;
              if(G==0)
                begin
                BF6<=10;
                  if(F==0)
                    begin
                      BF5<=10;
                       if(E==0)
                          begin
                            BF4<=10;
                               if(D==0)
                                begin
                                  BF3<=10;
                                    if(C==0)
                                       begin
                                         BF2<=10;
                                           if(B==0)
                                              begin
                                                 BF1<=10;
                                               end
                                            else begin
                                                  BF1<=B;
                                                  end
                                          end
                                    else begin
                                         BF1<=B;
                                         BF2<=C;
                                         end
                                    end
                                     else
                                         begin
                                            BF1<=B;
                                            BF2<=C;
                                            BF3<=D;
                                          end
                                     end
                                   else
                                      begin
                                      BF1<=B;
                                      BF2<=C;
                                      BF3<=D;
                                      BF4<=E;
                                   end
                               end
                             else 
                             begin
                             BF1<=B;
                             BF2<=C;
                             BF3<=D;
                             BF4<=E;
                             BF5<=F;
                             end
                         end
                          else 
                               begin
                                BF1<=B;
                                BF2<=C;
                                BF3<=D;
                                BF4<=E;
                                BF5<=F;
                                BF6<=G;
                                end
                            end
                else
            begin
            BF1<=B;
            BF2<=C;
            BF3<=D;
            BF4<=E;
            BF5<=F;
            BF6<=G;
            BF7<=H;
          end
      end
endmodule