sel_counter.v

使用vriloge硬件描述语言设计数字频率计

module sel_counter(sel,clksel,A,B,C,D,E,F,G,H,SET);
input[3:0]A,B,C,D,E,F,G,H;
output[2:0]sel;
input clksel;
output[3:0]SET;
reg[3:0]SET;
reg[2:0]sel;
always @(posedge clksel)
     begin
         sel<=sel+1;
     end
always @(sel)
     begin
         if(sel==0)
            begin 
               SET<=A;
             end
         else if(sel==1)
              begin 
                  SET<=B;
               end
         else if(sel==2)
              begin  
                  SET<=C;
               end
         else if(sel==3) 
             begin 
                SET<=D;
             end
         else if(sel==4)
                begin
                   SET<=E;
                end
        else if(sel==5)
                begin 
                    SET<=F;
                 end
        else if(sel==6)
              begin 
                 SET<=G;
               end
        else if(sel==7)
              begin 
                   SET<=H;
               end
end
  endmodule