counter.v

使用vriloge硬件描述语言设计数字频率计

module counter(A,B,C,D,E,F,G,H,clkput,REST);
input clkput,REST;
output[3:0]A,B,C,D,E,F,G,H;
reg[3:0]A,B,C,D,E,F,G,H;
 always @( posedge clkput or negedge REST)
   begin  
    if(!REST)
          begin
               A<=0;
               B<=0;
               C<=0;
               D<=0;
               E<=0;
               F<=0;
               G<=0;
               H<=0;
          end
    else 
       begin
          if (A==9&&B==9&&C==9&&D==9&&E==9&&F==9&&G==9&&H==9)
           begin
           A<=0;
           B<=0;
           C<=0;
           D<=0;
           E<=0;
           F<=0;
           G<=0;
           H<=0;             
           end
   else if(A==9&&B==9&&C==9&&D==9&&E==9&&F==9&&G==9)
        begin
             A<=0;
             B<=0;
             C<=0;
             D<=0;
             E<=0;
             F<=0;
             G<=0;
             H<=H+1;
            end
   else if(A==9&&B==9&&C==9&&D==9&&E==9&&F==9)
        begin
            A<=0;
            B<=0;
            C<=0;
            D<=0;
            E<=0;          
            D<=0;
            E<=0;
            F<=0;
            G<=G+1;
            end
    else if(A==9&&B==9&&C==9&&D==9&&E==9)
          begin
             A<=0;
             B<=0;
             C<=0;
             D<=0;
             E<=0;
             F<=F+1;
             end
      else if(A==9&&B==9&&C==9&&D==9)
                begin
               A<=0;
               B<=0;
               C<=0;
               D<=0;
               E<=E+1;
               end
            else if(A==9&&B==9&&C==9)
                begin
                A<=0;
                B<=0;
                C<=0;
                D<=D+1;
                end
             else if(A==9&&B==9)
                begin
                  A<=0;
                  B<=0;
                  C<=C+1;
                  end
             else if(A==9)
                 begin
                   A<=0;
                   B<=B+1;
                   end
             else
                begin
                  A<=A+1;
                end

     end
end
endmodule