sel_counter.rpt

使用vriloge硬件描述语言设计数字频率计

-- Node name is ':129' 
-- Equation name is '_LC5_A23', type is buried 
_LC5_A23 = LCELL( _EQ013);
  _EQ013 =  _LC2_A20 & !_LC7_A22
         #  H1 &  _LC7_A22;

-- Node name is ':130' 
-- Equation name is '_LC3_A23', type is buried 
_LC3_A23 = LCELL( _EQ014);
  _EQ014 = !_LC7_A22 &  _LC8_A19
         #  H0 &  _LC7_A22;

-- Node name is ':135' 
-- Equation name is '_LC2_A13', type is buried 
_LC2_A13 = LCELL( _EQ015);
  _EQ015 =  _LC1_A13 & !_LC6_A22
         #  G3 &  _LC6_A22;

-- Node name is ':136' 
-- Equation name is '_LC2_A16', type is buried 
_LC2_A16 = LCELL( _EQ016);
  _EQ016 =  _LC1_A16 & !_LC6_A22
         #  G2 &  _LC6_A22;

-- Node name is ':137' 
-- Equation name is '_LC6_A23', type is buried 
_LC6_A23 = LCELL( _EQ017);
  _EQ017 =  _LC5_A23 & !_LC6_A22
         #  G1 &  _LC6_A22;

-- Node name is ':138' 
-- Equation name is '_LC4_A23', type is buried 
_LC4_A23 = LCELL( _EQ018);
  _EQ018 =  _LC3_A23 & !_LC6_A22
         #  G0 &  _LC6_A22;

-- Node name is ':143' 
-- Equation name is '_LC3_A13', type is buried 
_LC3_A13 = LCELL( _EQ019);
  _EQ019 =  _LC2_A13 & !_LC5_A22
         #  F3 &  _LC5_A22;

-- Node name is ':144' 
-- Equation name is '_LC3_A16', type is buried 
_LC3_A16 = LCELL( _EQ020);
  _EQ020 =  _LC2_A16 & !_LC5_A22
         #  F2 &  _LC5_A22;

-- Node name is ':145' 
-- Equation name is '_LC7_A23', type is buried 
_LC7_A23 = LCELL( _EQ021);
  _EQ021 = !_LC5_A22 &  _LC6_A23
         #  F1 &  _LC5_A22;

-- Node name is ':146' 
-- Equation name is '_LC1_A23', type is buried 
_LC1_A23 = LCELL( _EQ022);
  _EQ022 =  _LC4_A23 & !_LC5_A22
         #  F0 &  _LC5_A22;

-- Node name is ':151' 
-- Equation name is '_LC4_A13', type is buried 
_LC4_A13 = LCELL( _EQ023);
  _EQ023 =  _LC3_A13 & !_LC6_A19
         #  E3 &  _LC6_A19;

-- Node name is ':152' 
-- Equation name is '_LC4_A16', type is buried 
_LC4_A16 = LCELL( _EQ024);
  _EQ024 =  _LC3_A16 & !_LC6_A19
         #  E2 &  _LC6_A19;

-- Node name is ':153' 
-- Equation name is '_LC8_A23', type is buried 
_LC8_A23 = LCELL( _EQ025);
  _EQ025 = !_LC6_A19 &  _LC7_A23
         #  E1 &  _LC6_A19;

-- Node name is ':154' 
-- Equation name is '_LC2_A19', type is buried 
_LC2_A19 = LCELL( _EQ026);
  _EQ026 =  _LC1_A23 & !_LC6_A19
         #  E0 &  _LC6_A19;

-- Node name is ':159' 
-- Equation name is '_LC6_A13', type is buried 
_LC6_A13 = LCELL( _EQ027);
  _EQ027 =  _LC4_A13 & !_LC4_A22
         #  D3 &  _LC4_A22;

-- Node name is ':160' 
-- Equation name is '_LC5_A16', type is buried 
_LC5_A16 = LCELL( _EQ028);
  _EQ028 =  _LC4_A16 & !_LC4_A22
         #  D2 &  _LC4_A22;

-- Node name is ':161' 
-- Equation name is '_LC2_A23', type is buried 
_LC2_A23 = LCELL( _EQ029);
  _EQ029 = !_LC4_A22 &  _LC8_A23
         #  D1 &  _LC4_A22;

-- Node name is ':162' 
-- Equation name is '_LC4_A19', type is buried 
_LC4_A19 = LCELL( _EQ030);
  _EQ030 =  _LC2_A19 & !_LC4_A22
         #  D0 &  _LC4_A22;

-- Node name is ':167' 
-- Equation name is '_LC7_A13', type is buried 
_LC7_A13 = LCELL( _EQ031);
  _EQ031 = !_LC3_A22 &  _LC6_A13
         #  C3 &  _LC3_A22;

-- Node name is ':168' 
-- Equation name is '_LC6_A16', type is buried 
_LC6_A16 = LCELL( _EQ032);
  _EQ032 = !_LC3_A22 &  _LC5_A16
         #  C2 &  _LC3_A22;

-- Node name is ':169' 
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = LCELL( _EQ033);
  _EQ033 =  _LC2_A23 & !_LC3_A22
         #  C1 &  _LC3_A22;

-- Node name is ':170' 
-- Equation name is '_LC5_A19', type is buried 
_LC5_A19 = LCELL( _EQ034);
  _EQ034 = !_LC3_A22 &  _LC4_A19
         #  C0 &  _LC3_A22;

-- Node name is ':175' 
-- Equation name is '_LC8_A13', type is buried 
_LC8_A13 = LCELL( _EQ035);
  _EQ035 = !_LC2_A22 &  _LC7_A13
         #  B3 &  _LC2_A22;

-- Node name is ':176' 
-- Equation name is '_LC8_A16', type is buried 
_LC8_A16 = LCELL( _EQ036);
  _EQ036 = !_LC2_A22 &  _LC6_A16
         #  B2 &  _LC2_A22;

-- Node name is ':177' 
-- Equation name is '_LC3_A20', type is buried 
_LC3_A20 = LCELL( _EQ037);
  _EQ037 =  _LC1_A20 & !_LC2_A22
         #  B1 &  _LC2_A22;

-- Node name is ':178' 
-- Equation name is '_LC7_A19', type is buried 
_LC7_A19 = LCELL( _EQ038);
  _EQ038 = !_LC2_A22 &  _LC5_A19
         #  B0 &  _LC2_A22;

-- Node name is ':183' 
-- Equation name is '_LC5_A13', type is buried 
_LC5_A13 = LCELL( _EQ039);
  _EQ039 = !_LC1_A19 &  _LC8_A13
         #  A3 &  _LC1_A19;

-- Node name is ':184' 
-- Equation name is '_LC7_A16', type is buried 
_LC7_A16 = LCELL( _EQ040);
  _EQ040 = !_LC1_A19 &  _LC8_A16
         #  A2 &  _LC1_A19;

-- Node name is ':185' 
-- Equation name is '_LC2_A20', type is buried 
_LC2_A20 = LCELL( _EQ041);
  _EQ041 = !_LC1_A19 &  _LC3_A20
         #  A1 &  _LC1_A19;

-- Node name is ':186' 
-- Equation name is '_LC8_A19', type is buried 
_LC8_A19 = LCELL( _EQ042);
  _EQ042 = !_LC1_A19 &  _LC7_A19
         #  A0 &  _LC1_A19;



Project Information                                e:\datacont\sel_counter.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 20,099K