📄 sel_counter.rpt
字号:
7 - - A -- OUTPUT 0 1 0 0 sel0
8 - - A -- OUTPUT 0 1 0 0 sel1
5 - - A -- OUTPUT 0 1 0 0 sel2
10 - - A -- OUTPUT 0 1 0 0 SET0
6 - - A -- OUTPUT 0 1 0 0 SET1
23 - - C -- OUTPUT 0 1 0 0 SET2
22 - - C -- OUTPUT 0 1 0 0 SET3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\datacont\sel_counter.rpt
sel_counter
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 22 DFFE + 0 2 1 8 :44
- 8 - A 22 DFFE + 0 1 1 9 :45
- 3 - A 19 DFFE + 0 0 1 10 :46
- 1 - A 19 AND2 0 3 0 4 :47
- 2 - A 22 AND2 0 3 0 4 :56
- 3 - A 22 AND2 0 3 0 4 :65
- 4 - A 22 AND2 0 3 0 4 :74
- 6 - A 19 AND2 0 3 0 4 :83
- 5 - A 22 AND2 0 3 0 4 :93
- 6 - A 22 AND2 0 3 0 4 :103
- 7 - A 22 AND2 0 3 0 4 :113
- 1 - A 13 OR2 1 2 0 1 :127
- 1 - A 16 OR2 1 2 0 1 :128
- 5 - A 23 OR2 1 2 0 1 :129
- 3 - A 23 OR2 1 2 0 1 :130
- 2 - A 13 OR2 1 2 0 1 :135
- 2 - A 16 OR2 1 2 0 1 :136
- 6 - A 23 OR2 1 2 0 1 :137
- 4 - A 23 OR2 1 2 0 1 :138
- 3 - A 13 OR2 1 2 0 1 :143
- 3 - A 16 OR2 1 2 0 1 :144
- 7 - A 23 OR2 1 2 0 1 :145
- 1 - A 23 OR2 1 2 0 1 :146
- 4 - A 13 OR2 1 2 0 1 :151
- 4 - A 16 OR2 1 2 0 1 :152
- 8 - A 23 OR2 1 2 0 1 :153
- 2 - A 19 OR2 1 2 0 1 :154
- 6 - A 13 OR2 1 2 0 1 :159
- 5 - A 16 OR2 1 2 0 1 :160
- 2 - A 23 OR2 1 2 0 1 :161
- 4 - A 19 OR2 1 2 0 1 :162
- 7 - A 13 OR2 1 2 0 1 :167
- 6 - A 16 OR2 1 2 0 1 :168
- 1 - A 20 OR2 1 2 0 1 :169
- 5 - A 19 OR2 1 2 0 1 :170
- 8 - A 13 OR2 1 2 0 1 :175
- 8 - A 16 OR2 1 2 0 1 :176
- 3 - A 20 OR2 1 2 0 1 :177
- 7 - A 19 OR2 1 2 0 1 :178
- 5 - A 13 OR2 1 2 1 1 :183
- 7 - A 16 OR2 1 2 1 1 :184
- 2 - A 20 OR2 1 2 1 1 :185
- 8 - A 19 OR2 1 2 1 1 :186
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\datacont\sel_counter.rpt
sel_counter
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 20/ 96( 20%) 0/ 48( 0%) 23/ 48( 47%) 5/16( 31%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\datacont\sel_counter.rpt
sel_counter
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 clksel
Device-Specific Information: e:\datacont\sel_counter.rpt
sel_counter
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
clksel : INPUT;
C0 : INPUT;
C1 : INPUT;
C2 : INPUT;
C3 : INPUT;
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
E0 : INPUT;
E1 : INPUT;
E2 : INPUT;
E3 : INPUT;
F0 : INPUT;
F1 : INPUT;
F2 : INPUT;
F3 : INPUT;
G0 : INPUT;
G1 : INPUT;
G2 : INPUT;
G3 : INPUT;
H0 : INPUT;
H1 : INPUT;
H2 : INPUT;
H3 : INPUT;
-- Node name is 'sel0'
-- Equation name is 'sel0', type is output
sel0 = _LC3_A19;
-- Node name is 'sel1'
-- Equation name is 'sel1', type is output
sel1 = _LC8_A22;
-- Node name is 'sel2'
-- Equation name is 'sel2', type is output
sel2 = _LC1_A22;
-- Node name is 'SET0'
-- Equation name is 'SET0', type is output
SET0 = _LC8_A19;
-- Node name is 'SET1'
-- Equation name is 'SET1', type is output
SET1 = _LC2_A20;
-- Node name is 'SET2'
-- Equation name is 'SET2', type is output
SET2 = _LC7_A16;
-- Node name is 'SET3'
-- Equation name is 'SET3', type is output
SET3 = _LC5_A13;
-- Node name is ':44'
-- Equation name is '_LC1_A22', type is buried
_LC1_A22 = DFFE( _EQ001, GLOBAL( clksel), VCC, VCC, VCC);
_EQ001 = _LC1_A22 & !_LC8_A22
# _LC1_A22 & !_LC3_A19
# !_LC1_A22 & _LC3_A19 & _LC8_A22;
-- Node name is ':45'
-- Equation name is '_LC8_A22', type is buried
_LC8_A22 = DFFE( _EQ002, GLOBAL( clksel), VCC, VCC, VCC);
_EQ002 = !_LC3_A19 & _LC8_A22
# _LC3_A19 & !_LC8_A22;
-- Node name is ':46'
-- Equation name is '_LC3_A19', type is buried
_LC3_A19 = DFFE(!_LC3_A19, GLOBAL( clksel), VCC, VCC, VCC);
-- Node name is ':47'
-- Equation name is '_LC1_A19', type is buried
_LC1_A19 = LCELL( _EQ003);
_EQ003 = !_LC1_A22 & !_LC3_A19 & !_LC8_A22;
-- Node name is ':56'
-- Equation name is '_LC2_A22', type is buried
_LC2_A22 = LCELL( _EQ004);
_EQ004 = !_LC1_A22 & _LC3_A19 & !_LC8_A22;
-- Node name is ':65'
-- Equation name is '_LC3_A22', type is buried
_LC3_A22 = LCELL( _EQ005);
_EQ005 = !_LC1_A22 & !_LC3_A19 & _LC8_A22;
-- Node name is ':74'
-- Equation name is '_LC4_A22', type is buried
_LC4_A22 = LCELL( _EQ006);
_EQ006 = !_LC1_A22 & _LC3_A19 & _LC8_A22;
-- Node name is ':83'
-- Equation name is '_LC6_A19', type is buried
_LC6_A19 = LCELL( _EQ007);
_EQ007 = _LC1_A22 & !_LC3_A19 & !_LC8_A22;
-- Node name is ':93'
-- Equation name is '_LC5_A22', type is buried
_LC5_A22 = LCELL( _EQ008);
_EQ008 = _LC1_A22 & _LC3_A19 & !_LC8_A22;
-- Node name is ':103'
-- Equation name is '_LC6_A22', type is buried
_LC6_A22 = LCELL( _EQ009);
_EQ009 = _LC1_A22 & !_LC3_A19 & _LC8_A22;
-- Node name is ':113'
-- Equation name is '_LC7_A22', type is buried
_LC7_A22 = LCELL( _EQ010);
_EQ010 = _LC1_A22 & _LC3_A19 & _LC8_A22;
-- Node name is ':127'
-- Equation name is '_LC1_A13', type is buried
_LC1_A13 = LCELL( _EQ011);
_EQ011 = _LC5_A13 & !_LC7_A22
# H3 & _LC7_A22;
-- Node name is ':128'
-- Equation name is '_LC1_A16', type is buried
_LC1_A16 = LCELL( _EQ012);
_EQ012 = _LC7_A16 & !_LC7_A22
# H2 & _LC7_A22;
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