_primary.vhd

来自「自己今年的毕业设计DDS波形发生器,有正弦波,方波,三角波,锯齿波.」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity mux4to1 is
    port(
        mux4_sel        : in     vl_logic_vector(1 downto 0);
        mux4_a          : in     vl_logic_vector(7 downto 0);
        mux4_b          : in     vl_logic_vector(7 downto 0);
        mux4_c          : in     vl_logic_vector(7 downto 0);
        mux4_d          : in     vl_logic_vector(7 downto 0);
        mux4_out        : out    vl_logic_vector(7 downto 0)
    );
end mux4to1;