_primary.vhd

来自「自己今年的毕业设计DDS波形发生器,有正弦波,方波,三角波,锯齿波.」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity sine is
    port(
        sine_acc_add    : in     vl_logic_vector(9 downto 0);
        sine_phase_add  : in     vl_logic_vector(9 downto 0);
        cin             : in     vl_logic;
        clk             : in     vl_logic;
        clr             : in     vl_logic;
        en              : in     vl_logic;
        sine_sel        : in     vl_logic;
        sine_data       : out    vl_logic_vector(7 downto 0)
    );
end sine;