_primary.vhd

自己今年的毕业设计DDS波形发生器,有正弦波,方波,三角波,锯齿波.

library verilog;
use verilog.vl_types.all;
entity myself_rec is
    port(
        clk             : in     vl_logic;
        myfreq_con      : out    vl_logic_vector(31 downto 0);
        myflag          : out    vl_logic_vector(1 downto 0);
        mycin           : out    vl_logic;
        myclr           : out    vl_logic;
        myen            : out    vl_logic;
        myphase_con     : out    vl_logic_vector(9 downto 0);
        mysel2to1       : out    vl_logic
    );
end myself_rec;