frequency_div.vhd

来自「通信基带信号发生器的设计」· VHDL 代码 · 共 41 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY FREQUENCY_DIV IS
PORT(  CLK,ENA_DIV:IN STD_LOGIC;
       CLK_OUT:OUT STD_LOGIC
     );
END ENTITY;

ARCHITECTURE DATAFLOW OF FREQUENCY_DIV IS

SIGNAL COUNT:INTEGER RANGE 0 TO 99:=0;


BEGIN

PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
     IF COUNT=0 THEN
   CLK_OUT<='0';
    ELSIF COUNT=50 THEN
   CLK_OUT<='1';
     END IF;
END IF;
END PROCESS;

PROCESS(CLK)
BEGIN
IF ENA_DIV='1' THEN
 IF(CLK'EVENT AND CLK='1') THEN
    IF COUNT=99 THEN
      COUNT<=0;
    ELSE
    COUNT<=COUNT+1;
    END IF;
 END IF;
END IF;
END PROCESS;
END;