sanjiao.vhd

通信基带信号发生器的设计

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 

entity sanjiao is 
port( en,clk:in std_logic; 
	  co:out std_logic_vector(9 downto 0));              
end sanjiao; 

architecture behav of sanjiao is 
   signal b:std_logic; 
   signal c:std_logic_vector(9 downto 0):="0000000000"; 
begin 

process(clk) 
begin
if en='1' then 
	if (clk'event and clk='1') then 
		if(b='0') then 
			if(c=1023) then 
				b<='1'; 
				c<="1111111110";
			else
				c<=c+'1'; 			
			end if; 
		elsif(b='1') then 
			if(c=1) then 
				b<='0'; 
				c<="0000000000";
			else
				c<=c-'1'; 
			end if; 
		end if; 
		co<=c; 
	end if;
end if;	 
end process; 
end architecture;