signal.tan.qmsg

通信基带信号发生器的设计

{ "Info" "ITAN_NO_REG2REG_EXIST" "EN " "Info: No valid register-to-register data paths exist for clock \"EN\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "TXD register register PARALLEL:inst6\|TEMP1\[6\] PARALLEL:inst6\|TEMP0\[6\] 275.03 MHz Internal " "Info: Clock \"TXD\" Internal fmax is restricted to 275.03 MHz between source register \"PARALLEL:inst6\|TEMP1\[6\]\" and destination register \"PARALLEL:inst6\|TEMP0\[6\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.669 ns + Longest register register " "Info: + Longest register to register delay is 2.669 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PARALLEL:inst6\|TEMP1\[6\] 1 REG LC_X26_Y10_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y10_N4; Fanout = 3; REG Node = 'PARALLEL:inst6\|TEMP1\[6\]'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PARALLEL:inst6|TEMP1[6] } "NODE_NAME" } } { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.360 ns) + CELL(0.309 ns) 2.669 ns PARALLEL:inst6\|TEMP0\[6\] 2 REG LC_X22_Y14_N9 1 " "Info: 2: + IC(2.360 ns) + CELL(0.309 ns) = 2.669 ns; Loc. = LC_X22_Y14_N9; Fanout = 1; REG Node = 'PARALLEL:inst6\|TEMP0\[6\]'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.669 ns" { PARALLEL:inst6|TEMP1[6] PARALLEL:inst6|TEMP0[6] } "NODE_NAME" } } { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 11.58 % ) " "Info: Total cell delay = 0.309 ns ( 11.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.360 ns ( 88.42 % ) " "Info: Total interconnect delay = 2.360 ns ( 88.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.669 ns" { PARALLEL:inst6|TEMP1[6] PARALLEL:inst6|TEMP0[6] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.669 ns" { PARALLEL:inst6|TEMP1[6] PARALLEL:inst6|TEMP0[6] } { 0.000ns 2.360ns } { 0.000ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.021 ns - Smallest " "Info: - Smallest clock skew is 0.021 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TXD destination 7.751 ns + Shortest register " "Info: + Shortest clock path from clock \"TXD\" to destination register is 7.751 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns TXD 1 CLK PIN_206 32 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_206; Fanout = 32; CLK Node = 'TXD'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TXD } "NODE_NAME" } } { "FINAL.bdf" "" { Schematic "D:/SIGNAL_FBSJB/SIGNAL/FINAL.bdf" { { 448 -920 -752 464 "TXD" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.565 ns) + CELL(0.711 ns) 7.751 ns PARALLEL:inst6\|TEMP0\[6\] 2 REG LC_X22_Y14_N9 1 " "Info: 2: + IC(5.565 ns) + CELL(0.711 ns) = 7.751 ns; Loc. = LC_X22_Y14_N9; Fanout = 1; REG Node = 'PARALLEL:inst6\|TEMP0\[6\]'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.276 ns" { TXD PARALLEL:inst6|TEMP0[6] } "NODE_NAME" } } { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 28.20 % ) " "Info: Total cell delay = 2.186 ns ( 28.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.565 ns ( 71.80 % ) " "Info: Total interconnect delay = 5.565 ns ( 71.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.751 ns" { TXD PARALLEL:inst6|TEMP0[6] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "7.751 ns" { TXD TXD~out0 PARALLEL:inst6|TEMP0[6] } { 0.000ns 0.000ns 5.565ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TXD source 7.730 ns - Longest register " "Info: - Longest clock path from clock \"TXD\" to source register is 7.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns TXD 1 CLK PIN_206 32 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_206; Fanout = 32; CLK Node = 'TXD'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TXD } "NODE_NAME" } } { "FINAL.bdf" "" { Schematic "D:/SIGNAL_FBSJB/SIGNAL/FINAL.bdf" { { 448 -920 -752 464 "TXD" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.544 ns) + CELL(0.711 ns) 7.730 ns PARALLEL:inst6\|TEMP1\[6\] 2 REG LC_X26_Y10_N4 3 " "Info: 2: + IC(5.544 ns) + CELL(0.711 ns) = 7.730 ns; Loc. = LC_X26_Y10_N4; Fanout = 3; REG Node = 'PARALLEL:inst6\|TEMP1\[6\]'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.255 ns" { TXD PARALLEL:inst6|TEMP1[6] } "NODE_NAME" } } { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 28.28 % ) " "Info: Total cell delay = 2.186 ns ( 28.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.544 ns ( 71.72 % ) " "Info: Total interconnect delay = 5.544 ns ( 71.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.730 ns" { TXD PARALLEL:inst6|TEMP1[6] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "7.730 ns" { TXD TXD~out0 PARALLEL:inst6|TEMP1[6] } { 0.000ns 0.000ns 5.544ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.751 ns" { TXD PARALLEL:inst6|TEMP0[6] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "7.751 ns" { TXD TXD~out0 PARALLEL:inst6|TEMP0[6] } { 0.000ns 0.000ns 5.565ns } { 0.000ns 1.475ns 0.711ns } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.730 ns" { TXD PARALLEL:inst6|TEMP1[6] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "7.730 ns" { TXD TXD~out0 PARALLEL:inst6|TEMP1[6] } { 0.000ns 0.000ns 5.544ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.669 ns" { PARALLEL:inst6|TEMP1[6] PARALLEL:inst6|TEMP0[6] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.669 ns" { PARALLEL:inst6|TEMP1[6] PARALLEL:inst6|TEMP0[6] } { 0.000ns 2.360ns } { 0.000ns 0.309ns } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.751 ns" { TXD PARALLEL:inst6|TEMP0[6] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "7.751 ns" { TXD TXD~out0 PARALLEL:inst6|TEMP0[6] } { 0.000ns 0.000ns 5.565ns } { 0.000ns 1.475ns 0.711ns } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.730 ns" { TXD PARALLEL:inst6|TEMP1[6] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "7.730 ns" { TXD TXD~out0 PARALLEL:inst6|TEMP1[6] } { 0.000ns 0.000ns 5.544ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PARALLEL:inst6|TEMP0[6] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { PARALLEL:inst6|TEMP0[6] } {  } {  } } } { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "PLL:inst4\|altpll:altpll_component\|_clk0 register NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_dxx:ux002\|dxxpdo\[7\] register NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_gal:ux009\|rom_add\[2\] 859 ps " "Info: Minimum slack time is 859 ps for clock \"PLL:inst4\|altpll:altpll_component\|_clk0\" between source register \"NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_dxx:ux002\|dxxpdo\[7\]\" and destination register \"NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_gal:ux009\|rom_add\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.650 ns + Shortest register register " "Info: + Shortest register to register delay is 0.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_dxx:ux002\|dxxpdo\[7\] 1 REG LC_X19_Y15_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y15_N7; Fanout = 1; REG Node = 'NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_dxx:ux002\|dxxpdo\[7\]'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7] } "NODE_NAME" } } { "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_dxx.v" "" { Text "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_dxx.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.535 ns) + CELL(0.115 ns) 0.650 ns NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_gal:ux009\|rom_add\[2\] 2 REG LC_X19_Y15_N6 6 " "Info: 2: + IC(0.535 ns) + CELL(0.115 ns) = 0.650 ns; Loc. = LC_X19_Y15_N6; Fanout = 6; REG Node = 'NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_gal:ux009\|rom_add\[2\]'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.650 ns" { NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7] NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_gal:ux009|rom_add[2] } "NODE_NAME" } } { "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_gal.v" "" { Text "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_gal.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 17.69 % ) " "Info: Total cell delay = 0.115 ns ( 17.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.535 ns ( 82.31 % ) " "Info: Total interconnect delay = 0.535 ns ( 82.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.650 ns" { NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7] NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_gal:ux009|rom_add[2] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "0.650 ns" { NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7] NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_gal:ux009|rom_add[2] } { 0.000ns 0.535ns } { 0.000ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.885 ns " "Info: + Latch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLL:inst4\|altpll:altpll_component\|_clk0 5.000 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"PLL:inst4\|altpll:altpll_component\|_clk0\" is 5.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLL:inst4\|altpll:altpll_component\|_clk0 5.000 ns -1.885 ns  50 " "Info: Clock period of Source clock \"PLL:inst4\|altpll:altpll_component\|_clk0\" is 5.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst4\|altpll:altpll_component\|_clk0 destination 2.405 ns + Longest register " "Info: + Longest clock path from clock \"PLL:inst4\|altpll:altpll_component\|_clk0\" to destination register is 2.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_1 675 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 675; CLK Node = 'PLL:inst4\|altpll:altpll_component\|_clk0'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/eda/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.694 ns) + CELL(0.711 ns) 2.405 ns NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_gal:ux009\|rom_add\[2\] 2 REG LC_X19_Y15_N6 6 " "Info: 2: + IC(1.694 ns) + CELL(0.711 ns) = 2.405 ns; Loc. = LC_X19_Y15_N6; Fanout = 6; REG Node = 'NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_gal:ux009\|rom_add\[2\]'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_gal:ux009|rom_add[2] } "NODE_NAME" } } { "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_gal.v" "" { Text "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_gal.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.56 % ) " "Info: Total cell delay = 0.711 ns ( 29.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.694 ns ( 70.44 % ) " "Info: Total interconnect delay = 1.694 ns ( 70.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_gal:ux009|rom_add[2] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_gal:ux009|rom_add[2] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst4\|altpll:altpll_component\|_clk0 source 2.405 ns - Shortest register " "Info: - Shortest clock path from clock \"PLL:inst4\|altpll:altpll_component\|_clk0\" to source register is 2.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_1 675 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 675; CLK Node = 'PLL:inst4\|altpll:altpll_component\|_clk0'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/eda/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.694 ns) + CELL(0.711 ns) 2.405 ns NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_dxx:ux002\|dxxpdo\[7\] 2 REG LC_X19_Y15_N7 1 " "Info: 2: + IC(1.694 ns) + CELL(0.711 ns) = 2.405 ns; Loc. = LC_X19_Y15_N7; Fanout = 1; REG Node = 'NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_dxx:ux002\|dxxpdo\[7\]'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7] } "NODE_NAME" } } { "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_dxx.v" "" { Text "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_dxx.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.56 % ) " "Info: Total cell delay = 0.711 ns ( 29.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.694 ns ( 70.44 % ) " "Info: Total interconnect delay = 1.694 ns ( 70.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_gal:ux009|rom_add[2] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_gal:ux009|rom_add[2] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_dxx.v" "" { Text "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_dxx.v" 62 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_gal.v" "" { Text "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_gal.v" 38 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_gal:ux009|rom_add[2] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_gal:ux009|rom_add[2] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.650 ns" { NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7] NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_gal:ux009|rom_add[2] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "0.650 ns" { NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7] NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_gal:ux009|rom_add[2] } { 0.000ns 0.535ns } { 0.000ns 0.115ns } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_gal:ux009|rom_add[2] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_gal:ux009|rom_add[2] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "CLK_IN register xulie:inst12\|u1 register xulie:inst12\|u2 861 ps " "Info: Minimum slack time is 861 ps for clock \"CLK_IN\" between source register \"xulie:inst12\|u1\" and destination register \"xulie:inst12\|u2\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.652 ns + Shortest register register " "Info: + Shortest register to register delay is 0.652 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns xulie:inst12\|u1 1 REG LC_X29_Y5_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y5_N9; Fanout = 1; REG Node = 'xulie:inst12\|u1'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { xulie:inst12|u1 } "NODE_NAME" } } { "xulie.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/xulie.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.537 ns) + CELL(0.115 ns) 0.652 ns xulie:inst12\|u2 2 REG LC_X29_Y5_N5 2 " "Info: 2: + IC(0.537 ns) + CELL(0.115 ns) = 0.652 ns; Loc. = LC_X29_Y5_N5; Fanout = 2; REG Node = 'xulie:inst12\|u2'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.652 ns" { xulie:inst12|u1 xulie:inst12|u2 } "NODE_NAME" } } { "xulie.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/xulie.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 17.64 % ) " "Info: Total cell delay = 0.115 ns ( 17.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.537 ns ( 82.36 % ) " "Info: Total interconnect delay = 0.537 ns ( 82.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.652 ns" { xulie:inst12|u1 xulie:inst12|u2 } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "0.652 ns" { xulie:inst12|u1 xulie:inst12|u2 } { 0.000ns 0.537ns } { 0.000ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK_IN 20.000 ns 0.000 ns  50 " "